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MPC961PFAR2 PDF预览

MPC961PFAR2

更新时间: 2024-09-23 21:14:31
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件
页数 文件大小 规格书
10页 348K
描述
961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32

MPC961PFAR2 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFP包装说明:PLASTIC, LQFP-32
针数:32Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.22
其他特性:ALSO OPERATE AT 3.3V SUPPLY系列:961
输入调节:DIFFERENTIALJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.02 A
湿度敏感等级:2功能数量:1
反相输出次数:端子数量:32
实输出次数:17最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):220
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm最小 fmax:100 MHz
Base Number Matches:1

MPC961PFAR2 数据手册

 浏览型号MPC961PFAR2的Datasheet PDF文件第2页浏览型号MPC961PFAR2的Datasheet PDF文件第3页浏览型号MPC961PFAR2的Datasheet PDF文件第4页浏览型号MPC961PFAR2的Datasheet PDF文件第5页浏览型号MPC961PFAR2的Datasheet PDF文件第6页浏览型号MPC961PFAR2的Datasheet PDF文件第7页 
Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MPC961P/D  
ꢄ ꢆꢇ ꢈꢆꢉꢊ ꢋ ꢌ ꢍ ꢎ ꢍ ꢏꢆ ꢐꢍ ꢉ ꢋꢑ  
ꢒ ꢓ ꢔꢔꢍ ꢏ  
The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay  
buffer. With output frequencies of up to 200MHz, output skews of 150ps  
the device meets the needs of the most demanding clock tree applica-  
tions.  
LOW VOLTAGE  
Fully Integrated PLL  
Up to 200MHz I/O Frequency  
LVCMOS Outputs  
ZERO DELAY BUFFER  
Outputs Disable in High Impedance  
LVPECL Reference Clock Options  
LQFP Packaging  
50ps Cycle–Cycle Jitter  
150ps Output Skews  
The MPC961 is offered with two different input configurations. The  
MPC961C offers an LVCMOS reference clock while the MPC961P offers  
an LVPECL reference clock.  
When pulled high the OE pin will force all of the outputs (except QFB)  
into a high impedance state. Because the OE pin does not affect the QFB  
output, down stream clocks can be disabled without the internal PLL los-  
ing lock.  
5
FA SUFFIX  
32–LEAD LQFP PACKAGE  
CASE 873A  
The MPC961 is fully 2.5V or 3.3V compatible and requires no external  
loop filter components. All control inputs accept LVCMOS compatible lev-  
els and the outputs provide low impedance LVCMOS outputs capable of  
driving terminated 50W transmission lines. For series terminated lines the  
MPC961 can drive two lines per output giving the device an effective  
fanout of 1:36. The device is packaged in a 32 lead LQFP package to  
provide the optimum combination of board density and performance.  
ꢎꢖ ꢗ  
ꢯ ꢀ ꢨꢖ ꢤꢣꢖ ꢣꢖ ꢖ ꢤ ꢫꢫ ꢨꢢꢰꢤ ꢧ ꢢꢩꢥ ꢣ ꢣꢖ ꢰꢧ ꢢꢩꢥ ꢗ ꢩꢟ ꢱ ꢖꢧ ꢤ ꢢꢨꢣꢯ  
ꢁ ꢏ  
Figure 1. MPC961P Logic Diagram  
Rev 2  
486  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
For More Information On This Product,  
Go to: www.freescale.com  

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