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MPC953FAR2 PDF预览

MPC953FAR2

更新时间: 2024-09-23 21:20:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动输出元件逻辑集成电路
页数 文件大小 规格书
5页 106K
描述
PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32

MPC953FAR2 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.25其他特性:PLL BYPASS OPTION AVAILABLE
输入调节:DIFFERENTIALJESD-30 代码:S-PQFP-G32
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:8
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE传播延迟(tpd):7 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD宽度:7 mm
最小 fmax:50 MHzBase Number Matches:1

MPC953FAR2 数据手册

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ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MPC953/D  
The MPC953 is a 3.3V compatible, PLL based clock driver device tar-  
geted for high performance clock tree designs. With output frequencies of  
up to 110MHz and output skews of 150ps the MPC953 is ideal for the  
most demanding clock tree designs. The devices employ a fully differen-  
tial PLL design to minimize cycle–to–cycle and phase jitter.  
See Upgrade Product – MPC9653  
LOW VOLTAGE  
PLL CLOCK DRIVER  
Fully Integrated PLL  
Output Frequency up to 110MHz in PLL Mode  
Outputs Disable in High Impedance  
LQFP Packaging  
100ps Cycle–to–Cycle Jitter  
The MPC953 has a differential LVPECL reference input along with an  
external feedback input. These features make the MPC953 ideal for use  
as a zero delay, low skew fanout buffer. The device performance has  
been tuned and optimized for zero delay performance. The MR/OE input  
pin will reset the internal counters and tristate the output buffers when  
driven “high”.  
The MPC953 is fully 3.3V compatible and requires no external loop  
filter components. All control inputs accept LVCMOS or LVTTL compat-  
ible levels while the outputs provide LVCMOS levels with the ability to  
drive terminated 50transmission lines. For series terminated 50lines,  
each of the MPC953 outputs can drive two traces giving the device an  
effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead  
LQFP package to provide the optimum combination of board density and  
performance.  
5
FA SUFFIX  
32–LEAD LQFP PACKAGE  
CASE 873A  
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ꢓ ꢔꢔ ꢕ ꢖꢔ ꢔ ꢗꢘꢙ  
÷ꢚ  
÷ꢓ  
Figure 1. Logic Diagram  
Rev 3  
452  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  

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