MPC948L

更新时间： 2024-11-09 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
6页	110K
描述
LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP

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数据手册

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MPC948L 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC948L is a 1:12 low voltage clock distribution chip. The device

is pin and function compatible with the MPC948 with the added feature of

2.5V output capabilities. The device features the capability to select either

a differential LVPECL or a LVTTL compatible input. The 12 outputs are

2.5V LVCMOS or LVTTL compatible and feature the drive strength to

drive 50Ω series terminated transmission lines. With output–to–output

skews of 350ps, the MPC948L is ideal as a clock distribution chip for the

most demanding of synchronous systems.

LOW VOLTAGE

1:12 CLOCK

DISTRIBUTION CHIP

• Clock Distribution for Intel Microprocessors

• LVPECL or LVCMOS/LVTTL Clock Input

• 350ps Maximum Output–to–Output Skew

• Drives Up to 24 Independent Clock Lines

• Maximum Output Frequency of 150MHz

• Synchronous Output Enable

• Tristatable Outputs

FA SUFFIX

32–LEAD TQFP PACKAGE

CASE 873A–02

• 32–Lead TQFP Packaging

• 2.5V Output Capability

With an output impedance of approximately 7Ω, in both the HIGH and

LOW logic states, the output buffers of the MPC948L are ideal for driving

series terminated transmission lines. More specifically, each of the 12

MPC948L outputs can drive two series terminated 50Ω transmission

lines. With this capability, the MPC948L has an effective fanout of 1:24 in

applications where each line drives a single load.

The differential LVPECL inputs of the MPC948L allow the device to interface directly with a LVPECL fanout buffer like the

MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input

provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In

addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH

on the TTL_CLK_Sel pin will select the TTL level clock input.

All of the control inputs are LVCMOS/LVTTL compatible. The MPC948L provides a synchronous output enable control to allow

for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control

is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,

the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into

high impedance. Note that all of the MPC948L inputs have internal pullup resistors.

The 32–lead TQFP package was chosen to optimize performance, board space and cost of the device. The 32–lead TQFP

has a 7x7mm body size with a conservative 0.8mm pin spacing.

The MPC948L features two independent power supplies; VCCI and VCCO. The VCCI pin powers the internal core logic and

must be tied to 3.3V. The VCCO pin powers the output buffer and can be tied to either 2.5V or 3.3V.

This document contains information on a new product. Specifications and information herein are subject to

change without notice.

4/97

REV 0

Motorola, Inc. 1997

12 3 4 5 6

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与MPC948L相关器件

型号	品牌	获取价格	描述	数据表
MPC948LFA	MOTOROLA	获取价格	暂无描述
MPC949	MOTOROLA	获取价格	LOW VOLTAGE 1:15 PECL TO CMOS CLOCK DRIVER
MPC949FA	IDT	获取价格	Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC949FAR2	IDT	获取价格	Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC949FAR2	MOTOROLA	获取价格	MPC900 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, 10
MPC950	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC950FA	NXP	获取价格	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC
MPC950FA	IDT	获取价格	Processor Specific Clock Generator, 180MHz, CMOS, PQFP32, 7 X 7 MM, LQFP-32
MPC951	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC951FA	MOTOROLA	获取价格	LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP3

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