Datasheet > MPC949

MPC949

更新时间： 2024-09-22 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器
页数	文件大小	规格书
6页	131K
描述
LOW VOLTAGE 1:15 PECL TO CMOS CLOCK DRIVER

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MPC949 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15

outputs can be configured into a standard fanout buffer or into 1X and

1/2X combinations. The device features a low voltage PECL input, in

addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into

larger clock trees which utilize low skew PECL devices (see the

MC100LVE111 data sheet) in the lower branches of the tree. The fifteen

outputs were designed and optimized to drive 50Ω series or parallel

terminated transmission lines. With output to output skews of 300ps the

MPC949 is an ideal clock distribution chip for synchronous systems

which need a tight level of skew from a large number of outputs. For a

similar product with a smaller fanout and package consult the MPC946

data sheet.

LOW VOLTAGE

1:15 PECL TO CMOS

CLOCK DRIVER

• Clock Distribution for Pentium Systems with PCI

• Low Voltage PECL Clock Input

• 2 Selectable LVCMOS/LVTTL Clock Inputs

• 350ps Maximum Output to Output Skew

• Drives up to 30 Independent Clock Lines

• Maximum Output Frequency of 150MHz

• High Impedance Output Enable

FA SUFFIX

52–LEAD TQFP PACKAGE

CASE 848D–03

• 52–Lead TQFP Packaging

• 3.3V V

Supply

With an output impedance of approximately 7Ω, in both the HIGH and

the LOW logic states, the output buffers of the MPC949 are ideal for

driving series terminated transmission lines. More specifically each of the

15 MPC949 outputs can drive two series terminated transmission lines.

With this capability, the MPC949 has an effective fanout of 1:30 in

applications using point–to–point distribution schemes.

The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are

generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability

to allow the user to select the ratio of 1X outputs to 1/2X outputs.

Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to

provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the

TCLK1 input is selected. The PCLK_Sel input will select the PECL input clock when driven HIGH.

All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the

Dsel pins will select the 1X output. The MR/OE input will reset the internal flip flops and tristate the outputs when it is forced HIGH.

The MPC949 is fully 3.3V compatible. The 52 lead TQFP package was chosen to optimize performance, board space and cost

of the device. The 52–lead TQFP has a 10x10mm body size with a 0.65mm pin spacing.

Pentium is a trademark of Intel Corporation.

10/96

REV 1

Motorola, Inc. 1996

12 3 4 5 6

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与MPC949相关器件

型号	品牌	获取价格	描述	数据表
MPC949FA	IDT	获取价格	Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC949FAR2	IDT	获取价格	Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC949FAR2	MOTOROLA	获取价格	MPC900 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, 10
MPC950	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC950FA	NXP	获取价格	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC
MPC950FA	IDT	获取价格	Processor Specific Clock Generator, 180MHz, CMOS, PQFP32, 7 X 7 MM, LQFP-32
MPC951	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC951FA	MOTOROLA	获取价格	LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP3
MPC951FAR2	IDT	获取价格	PLL Based Clock Driver, 951 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC952	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER

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