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MPC9352AC PDF预览

MPC9352AC

更新时间: 2024-11-04 15:44:43
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
16页 338K
描述
9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, LQFP-32

MPC9352AC 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFP包装说明:LEAD FREE, LQFP-32
针数:32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.24
其他特性:ALSO OPERATES AT 3.3V SUPPLY系列:9352
输入调节:STANDARDJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.024 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:11最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
电源:2.5/3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mm最小 fmax:100 MHz
Base Number Matches:1

MPC9352AC 数据手册

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MPC9352  
Rev. 6, 1/2005  
Freescale Semiconductor  
Technical Data  
3.3 V/2.5 V 1:11 LVCMOS Zero  
Delay Clock Generator  
MPC9352  
The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL based clock generator  
targeted for high performance clock tree applications. With output frequencies up  
to 200 MHz and output skews lower than 200 ps, the device meets the needs of  
most demanding clock applications.  
LOW VOLTAGE  
3.3 V/2.5 V LVCMOS 1:11  
CLOCK GENERATOR  
Features  
Configurable 11 outputs LVCMOS PLL clock generator  
Fully integrated PLL  
Wide range of output clock frequency of 16.67 MHz to 200 MHz  
Multiplication of the input reference clock frequency by 3, 2, 1, 3 ÷ 2, 2 ÷ 3,  
1 ÷ 3 and 1 ÷ 2  
2.5 V and 3.3 V LVCMOS compatible  
Maximum output skew of 200 ps  
Supports zero-delay applications  
FA SUFFIX  
32-LEAD LQFP PACKAGE  
CASE 873A-03  
Designed for high-performance telecom, networking and computing  
applications  
32-lead LQFP package  
32-lead Pb-free Package Available  
Ambient Temperature Range –40°C to +85°C  
AC SUFFIX  
32-LEAD LQFP PACKAGE  
Pb-FREE PACKAGE  
CASE 873A-03  
Functional Description  
The MPC9352 is a fully 3.3 V or 2.5 V compatible PLL clock generator and  
clock driver. The device has the capability to generate output clock signals of  
16.67 to 200 MHz from external clock sources. The internal PLL is optimized for  
its frequency range and does not require external lock filter components. One output of the MPC9352 has to be connected to the  
PLL feedback input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL  
frequency multiplication factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to sit-  
uate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually for all three output  
banks by the FSELx pins supporting systems with different, but phase-aligned, clock frequencies.  
The PLL of the MPC9352 minimizes the propagation delay, and therefore, supports zero-delay applications. All inputs and out-  
puts are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50transmission lines. Alternatively, each  
output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.  
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The  
MPC9352 is packaged in a 32 ld LQFP.  
This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  
Freescale Confidential Proprietary, NDA Required / Preliminary  

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