MPC93R52FA

更新时间： 2024-02-20 07:46:26

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟发生器
页数	文件大小	规格书
16页	157K
描述
PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, PLASTIC, LQFP-32

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MPC93R52FA 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	,	针数：	32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.8
JESD-609代码：	e0	湿度敏感等级：	3
端子面层：	Tin/Lead (Sn85Pb15)	Base Number Matches：	1

MPC93R52FA 数据手册

Order Number: MPC93R52/D

Rev 2, 04/2003

SEMICONDUCTOR TECHNICAL DATA

The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator

targeted for high performance clock tree applications. With output

frequencies up to 240 MHz and output skews lower than 200 ps the

device meets the needs of most demanding clock applications.

LOW VOLTAGE

3.3V LVCMOS 1:11

CLOCK GENERATOR

Features

• Configurable 11 outputs LVCMOS PLL clock generator

• Fully integrated PLL

• Wide range of output clock frequency of 16.67 MHz to 240 MHz

• Multiplication of the input reference clock frequency by 3, 2, 1, 3 2,

3, 1 3 and 1

• 3.3V LVCMOS compatible

• Maximum output skew of 200 ps

• Supports zero–delay applications

• Designed for high–performance telecom, networking and computing

applications

• 32 lead LQFP package

• Ambient Temperature Range – 0°C to +70°C

• Pin and function compatible to the MPC952

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

Functional Description

The MPC93R52 is a fully 3.3V compatible PLL clock generator and

clock driver. The device has the capability to generate output clock

signals of 16.67 to 240 MHz from external clock sources. The internal PLL

optimized for its frequency range and does not require external look filter

components. One output of the MPC93R52 has to be connected to the

PLL feedback input FB_IN to close the external PLL feedback path. The

output divider of this output setting determines the PLL frequency

multiplication factor. This multiplication factor, F_RANGE and the

reference clock frequency must be selected to situate the VCO in its

specified lock range. The frequency of the clock outputs can be

configured individually for all three output banks by the FSELx pins

supporting systems with different but phase-aligned clock frequencies.

The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and

outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50Ω transmission lines. Alternatively,

each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.

The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The

MPC93R52 is package in a 32 ld LQFP.

Motorola, Inc. 2003

12 3 4 5 6 7...16

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与MPC93R52FA相关器件

型号	品牌	获取价格	描述	数据表
MPC93R52FAR2	IDT	获取价格	PLL Based Clock Driver, 93R Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLAST
MPC93R52FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32
MPC940	MOTOROLA	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940L	MOTOROLA	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940L	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LAC	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LACR2	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LFA	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LFAR2	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC941	MOTOROLA	获取价格	LOW VOLTAGE 1:27 CLOCK DISTRIBUTION CHIP

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