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MPC93H52AC PDF预览

MPC93H52AC

更新时间: 2024-01-14 20:05:41
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
16页 322K
描述
93H SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, LQFP-32

MPC93H52AC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
系列:93H输入调节:STANDARD
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.024 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:11
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.3 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:100 MHzBase Number Matches:1

MPC93H52AC 数据手册

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MPC93H52  
Rev. 5, 1/2005  
Freescale Semiconductor  
Technical Data  
3.3 V 1:11 LVCMOS Zero Delay  
Clock Generator  
MPC93H52  
The MPC93H52 is a 3.3 V compatible, 1:11 PLL based clock generator  
targeted for high performance clock tree applications. With output frequencies up  
to 240 MHz and output skews lower than 200 ps the device meets the needs of  
most demanding clock applications.  
LOW VOLTAGE  
3.3 V LVCMOS 1:11  
CLOCK GENERATOR  
Features  
Configurable 11 outputs LVCMOS PLL clock generator  
Fully integrated PLL  
Wide range of output clock frequency of 16.67 MHz to 240 MHz  
Multiplication of the input reference clock frequency by 3, 2, 1, 3÷2, 2÷3, 1÷3  
and 1÷2  
3.3 V LVCMOS compatible  
FA SUFFIX  
32-LEAD LQFP PACKAGE  
CASE 873A-03  
Maximum output skew of 200 ps  
Supports zero-delay applications  
Designed for high-performance telecom, networking and computing  
applications  
32-lead LQFP package  
AC SUFFIX  
32-LEAD LQFP PACKAGE  
Pb-FREE PACKAGE  
CASE 873A-03  
32-lead Pb-free Package Available  
Ambient Temperature Range — 0°C to +70°C  
Pin and function compatible to the MPC952  
Functional Description  
The MPC93H52 is a fully 3.3 V compatible PLL clock generator and clock driver. The device has the capability to generate  
output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL is optimized for its frequency range and  
does not require external lock filter components. One output of the MPC93H52 has to be connected to the PLL feedback input  
FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli-  
cation factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO in its  
specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx  
pins supporting systems with different but phase-aligned clock frequencies.  
The PLL of the MPC93H52 minimizes the propagation delay and, therefore, supports zero-delay applications. All inputs and  
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively,  
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.  
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The  
MPC93H52 is package in a 32-lead LQFP.  
This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  
Freescale Confidential Proprietary, NDA Required / Preliminary  

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