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MPC940 PDF预览

MPC940

更新时间: 2024-01-24 03:10:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟
页数 文件大小 规格书
5页 95K
描述
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP

MPC940 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:7 X 7 MM, LQFP-32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.76
其他特性:CAN ALSO OPERATE AT 3.3V SUPPLY系列:MPC900
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.02 A
湿度敏感等级:2功能数量:1
反相输出次数:端子数量:32
实输出次数:18最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:3.3 V
传播延迟(tpd):5.2 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mm最小 fmax:250 MHz
Base Number Matches:1

MPC940 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MPC940 is a 1:18 low voltage clock distribution chip. The device  
features the capability to select either a differential LVPECL or an LVTTL/  
LVCMOS compatible input. The 18 outputs are LVCMOS or LVTTL  
compatible and feature the drive strength to drive 50series or parallel  
terminated transmission lines. With output–to–output skews of 150ps, the  
MPC940 is ideal as a clock distribution chip for the most demanding of  
synchronous systems. For a similar product with a larger number of  
outputs, please consult the MPC941 data sheet.  
LOW VOLTAGE  
1:18 CLOCK  
DISTRIBUTION CHIP  
LVPECL or LVCMOS/LVTTL Clock Input  
150ps Maximum Targeted Output–to–Output Skew  
Drives Up to 36 Independent Clock Lines  
Maximum Output Frequency of 250MHz  
32–Lead TQFP Packaging  
3.3V V  
Supply Voltage  
CC  
FA SUFFIX  
32–LEAD TQFP PACKAGE  
CASE 873A–02  
With a low output impedance (20), in both the HIGH and LOW logic  
states, the output buffers of the MPC940 are ideal for driving series  
terminated transmission lines. More specifically, each of the 18 MPC940  
outputs can drive two series terminated 50transmission lines. With this  
capability, the MPC940 has an effective fanout of 1:36 in applications  
where each line drives a single load. With this level of fanout, the  
MPC940 provides enough copies of low skew clocks for most high  
performance synchronous systems.  
The differential LVPECL inputs of the MPC940 allow the device to interface directly with a LVPECL fanout buffer like the  
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input  
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In  
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH  
on the LVCMOS_CLK_Sel pin will select the TTL level clock input.  
The MPC940 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and  
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
6/97  
REV 0.2  
Motorola, Inc. 1997  

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