Datasheet > MPC940

MPC940

更新时间： 2024-11-03 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
5页	95K
描述
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP

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MPC940 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC940 is a 1:18 low voltage clock distribution chip. The device

features the capability to select either a differential LVPECL or an LVTTL/

LVCMOS compatible input. The 18 outputs are LVCMOS or LVTTL

compatible and feature the drive strength to drive 50Ω series or parallel

terminated transmission lines. With output–to–output skews of 150ps, the

MPC940 is ideal as a clock distribution chip for the most demanding of

synchronous systems. For a similar product with a larger number of

outputs, please consult the MPC941 data sheet.

LOW VOLTAGE

1:18 CLOCK

DISTRIBUTION CHIP

• LVPECL or LVCMOS/LVTTL Clock Input

• 150ps Maximum Targeted Output–to–Output Skew

• Drives Up to 36 Independent Clock Lines

• Maximum Output Frequency of 250MHz

• 32–Lead TQFP Packaging

• 3.3V V

Supply Voltage

FA SUFFIX

32–LEAD TQFP PACKAGE

CASE 873A–02

With a low output impedance (≈20Ω), in both the HIGH and LOW logic

states, the output buffers of the MPC940 are ideal for driving series

terminated transmission lines. More specifically, each of the 18 MPC940

outputs can drive two series terminated 50Ω transmission lines. With this

capability, the MPC940 has an effective fanout of 1:36 in applications

where each line drives a single load. With this level of fanout, the

MPC940 provides enough copies of low skew clocks for most high

performance synchronous systems.

The differential LVPECL inputs of the MPC940 allow the device to interface directly with a LVPECL fanout buffer like the

MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input

provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In

addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH

on the LVCMOS_CLK_Sel pin will select the TTL level clock input.

The MPC940 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and

cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.

This document contains information on a new product. Specifications and information herein are subject to

change without notice.

6/97

REV 0.2

Motorola, Inc. 1997

12 3 4 5

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与MPC940相关器件

型号	品牌	获取价格	描述	数据表
MPC940L	MOTOROLA	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940L	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LAC	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LACR2	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LFA	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LFAR2	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC941	MOTOROLA	获取价格	LOW VOLTAGE 1:27 CLOCK DISTRIBUTION CHIP
MPC941AE	NXP	获取价格	941 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7
MPC941AER2	IDT	获取价格	TQFP-48, Reel
MPC941FA	IDT	获取价格	Low Skew Clock Driver, 941 Series, 27 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7

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