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MPC941AER2 PDF预览

MPC941AER2

更新时间: 2024-10-02 05:42:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
12页 690K
描述
TQFP-48, Reel

MPC941AER2 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:LFQFP, QFP48,.35SQ,20针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.24
其他特性:ALSO OPERATE AT 3.3V SUPPLY系列:941
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.024 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:27最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:2.5/3.3 VProp。Delay @ Nom-Sup:2.9 ns
传播延迟(tpd):2.9 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:250 MHzBase Number Matches:1

MPC941AER2 数据手册

 浏览型号MPC941AER2的Datasheet PDF文件第2页浏览型号MPC941AER2的Datasheet PDF文件第3页浏览型号MPC941AER2的Datasheet PDF文件第4页浏览型号MPC941AER2的Datasheet PDF文件第5页浏览型号MPC941AER2的Datasheet PDF文件第6页浏览型号MPC941AER2的Datasheet PDF文件第7页 
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP  
MPC941  
The MPC941 is a 1:27 low voltage clock distribution chip. The device features  
the capability to select either a differential LVPECL or an LVCMOS compatible  
input. The 27 outputs are LVCMOS compatible and feature the drive strength to  
drive 50 series or parallel terminated transmission lines. With output-to-output  
skews of 250 ps, the MPC941 is ideal as a clock distribution chip for the most  
demanding of synchronous systems. For a similar product with a smaller number  
of outputs, please consult the MPC940 data sheet.  
LOW VOLTAGE 3.3 V/2.5 V  
1:27 CLOCK  
DISTRIBUTION CHIP  
LVPECL or LVCMOS Clock Input  
250 ps Maximum Output-to-Output Skew  
Drives Up to 54 Independent Clock Lines  
Maximum Output Frequency of 250 MHz  
High Impedance Output Enable  
Extended Temperature Range: –40°C to +85°C  
48-Lead LQFP Packaging  
48-Lead Pb-free Package Available  
3.3 V or 2.5 V VCC Supply Voltage  
With a low output impedance, in both the HIGH and LOW logic states, the  
FA SUFFIX  
48-LEAD LQFP PACKAGE  
CASE 932-03  
output buffers of the MPC941 are ideal for driving series terminated transmission  
lines. More specifically, each of the 27 MPC941 outputs can drive two series  
terminated 50 transmission lines. With this capability, the MPC941 has an  
effective fanout of 1:54. With this level of fanout, the MPC941 provides enough  
copies of low skew clocks for most high performance synchronous systems.  
The differential LVPECL inputs of the MPC941 allow the device to interface  
directly with an LVPECL fanout buffer like the MC100EP111 to build very wide  
clock fanout trees or to couple to a high frequency clock source. The LVCMOS  
input provides a more standard interface for applications requiring only a single  
clock distribution chip at relatively low frequencies. In addition, the two clock  
sources can be used as a test clock interface as well as the primary system clock.  
A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock  
input.  
AE SUFFIX  
48-LEAD LQFP PACKAGE  
Pb-FREE PACKAGE  
CASE 932-03  
The MPC941 is fully 3.3 V and 2.5 V compatible. The 48-lead LQFP package was chosen to optimize performance, board  
space and cost of the device. The 48-lead LQFP has a 7x7 mm body size.  
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP  
1
MPC941 REV. 8 APRIL 29, 2008  

MPC941AER2 替代型号

型号 品牌 替代类型 描述 数据表
CDC2516DGGR TI

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