Datasheet > MPC9446

MPC9446

更新时间： 2024-11-20 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
12页	220K
描述
2.5V and 3.3V LVCMOS Clock Fanout Buffer

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数据手册

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MPC9446 数据手册

MOTOROLA

Order Number: MPC9446/D

Rev 1, 03/2002

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

2.5V and 3.3V LVCMOS Clock

Fanout Buffer

MPC9446

The MPC9446 is a 2.5V and 3.3V compatible 1:10 clock distribution

buffer designed for low-voltage mid-range to high-performance telecom,

networking and computing applications. Both 3.3V, 2.5V and dual supply

voltages are supported for mixed-voltage applications. The MPC9446

offers 10 low-skew outputs and 2 selectable inputs for clock redundancy.

The outputs are configurable and support 1:1 and 1:2 output to input

frequency ratios. The MPC9446 is specified for the extended temperature

range of --40°C to 85°C.

LOW VOLTAGE SINGLE OR

DUAL SUPPLY 2.5V AND 3.3V

LVCMOS CLOCK

DISTRIBUTION BUFFER

Features

• Configurable 10 outputs LVCMOS clock distribution buffer

• Compatible to single, dual and mixed 3.3V/2.5V voltage supply

• Wide range output clock frequency up to 250 MHz

• Designed for mid-range to high-performance telecom, networking and

computer applications

• Supports applications requiring clock redundancy

• Max. output skew of 200 ps (150 ps within one bank)

• Selectable output configurations per output bank

• Tristable outputs

• 32 ld LQFP package

FA SUFFIX

LQFP PACKAGE

CASE 873A

• Ambient operating temperature range of --40 to 85°C

Functional Description

The MPC9446 is a full static fanout buffer design supporting clock

frequencies up to 250 MHz. The signals are generated and retimed

on-chip to ensure minimal skew between the three output banks. Two

independent LVCMOS compatible clock inputs are available. This feature

supports redundant clock sources or the addition of a test clock into the

system design. Each of the three output banks can be individually

supplied by 2.5V or 3.3V supporting mixed voltage applications. The

FSELx pins choose between division of the input reference frequency by

one or two. The frequency divider can be set individually for each of the

three output banks. The MPC9446 can be reset and the outputs are

disabled by deasserting the MR/OE pin (logic high state). Asserting

MR/OE will enable the outputs.

All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated

50 Ω transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible

inputs. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an

effective fanout of 1:20. The device is packaged in a 7x7 mm 32-lead LQFP package.

Fo¹r More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...12

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与MPC9446相关器件

型号	品牌	获取价格	描述	数据表
MPC9446AC	IDT	获取价格	3.3V and 2.5V, LVCMOS Clock Fanout Buffer
MPC9446ACR2	IDT	获取价格	3.3V and 2.5V, LVCMOS Clock Fanout Buffer
MPC9446ACR2	NXP	获取价格	9446 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9446FA	MOTOROLA	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, PLASTIC,
MPC9446FA	IDT	获取价格	Low Skew Clock Driver, 9446 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9446FAR2	NXP	获取价格	9446 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9446FAR2	MOTOROLA	获取价格	LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC9447	MOTOROLA	获取价格	3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
MPC9447	IDT	获取价格	3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
MPC9447ACR2	IDT	获取价格	9447 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTI

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