5秒后页面跳转
MPC9449 PDF预览

MPC9449

更新时间: 2024-09-22 22:51:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
12页 294K
描述
3.3V / 2.5 V 1:15 PECL/LVCMOS

MPC9449 数据手册

 浏览型号MPC9449的Datasheet PDF文件第2页浏览型号MPC9449的Datasheet PDF文件第3页浏览型号MPC9449的Datasheet PDF文件第4页浏览型号MPC9449的Datasheet PDF文件第5页浏览型号MPC9449的Datasheet PDF文件第6页浏览型号MPC9449的Datasheet PDF文件第7页 
Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order Number: MPC9449/D  
Rev 1, 08/2002  
The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer  
targeted for high performance clock tree applications. With output  
frequencies up to 200 MHz and output skews less than 200 ps the device  
meets the needs of the most demanding clock applications.  
3.3V/2.5V 1:15  
Features  
15 LVCMOS compatible clock outputs  
PECL/LVCMOS  
Two selectable LVCMOS and one differential LVPECL compatible clock  
inputs  
CLOCK FANOUT BUFFER  
Selectable output frequency divider (divide-by-one and divide-by-two)  
Maximum clock frequency of 200 MHz  
Maximum clock skew of 200 ps  
High-impedance output control  
3.3V or 2.5V power supply  
Drives up to 30 series terminated clock lines  
Ambient temperature range –40°C to +85°C  
52 lead LQFP packaging  
Supports clock distribution in networking, telecommunication and  
computing applications  
FA SUFFIX  
52 LEAD LQFP PACKAGE  
CASE 848D  
Pin and function compatible to MPC949  
Functional Description  
The MPC9449 is specifically designed to distribute LVCMOS  
compatible clock signals up to a frequency of 200 MHz. The device has  
15 identical outputs, organized in 4 output banks. Each output bank  
provides a retimed or frequency divided copy of the input signal with a  
near zero skew. The output buffer supports driving of 50terminated  
transmission lines on the incident edge: each output is capable of driving  
either one parallel terminated or two series terminated transmission lines.  
Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In  
addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input  
reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the  
OE control will force the outputs into high-impedance mode.  
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a  
2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9449 is pin and function compatible  
but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.  
For More Information On This Product,  
Motorola, Inc. 2002  
Go to: www.freescale.com  

与MPC9449相关器件

型号 品牌 获取价格 描述 数据表
MPC9449AER2 IDT

获取价格

9449 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC9449FA IDT

获取价格

Low Skew Clock Driver, 9449 Series, 15 True Output(s), 0 Inverted Output(s), ECL, PQFP52,
MPC9449FA MOTOROLA

获取价格

Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), ECL, PQFP52, PLASTIC, LQFP
MPC9449FAR2 IDT

获取价格

Low Skew Clock Driver, 9449 Series, 15 True Output(s), 0 Inverted Output(s), ECL, PQFP52,
MPC9449FAR2 MOTOROLA

获取价格

LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52
MPC94551 FREESCALE

获取价格

Low Voltage 1:4 CMOS Clock Buffer
MPC94551D FREESCALE

获取价格

Low Voltage 1:4 CMOS Clock Buffer
MPC94551DR2 FREESCALE

获取价格

Low Voltage 1:4 CMOS Clock Buffer
MPC94551EF FREESCALE

获取价格

Low Voltage 1:4 CMOS Clock Buffer
MPC94551EFR2 FREESCALE

获取价格

Low Voltage 1:4 CMOS Clock Buffer