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MPC948 PDF预览

MPC948

更新时间: 2024-09-22 22:51:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟
页数 文件大小 规格书
6页 104K
描述
LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP

MPC948 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MPC948 is a 1:12 low voltage clock distribution chip. The device  
features the capability to select either a differential LVPECL or a LVTTL  
compatible input. The 12 outputs are LVCMOS or LVTTL compatible and  
feature the drive strength to drive 50series terminated transmission  
lines. With output–to–output skews of 350ps, the MPC948 is ideal as a  
clock distribution chip for the most demanding of synchronous systems.  
For a similar product targeted at a lower price/performance point, please  
consult the MPC947 data sheet.  
LOW VOLTAGE  
1:12 CLOCK  
DISTRIBUTION CHIP  
Clock Distribution for PowerPC 620 L2 Cache  
LVPECL or LVCMOS/LVTTL Clock Input  
350ps Maximum Output–to–Output Skew  
Drives Up to 24 Independent Clock Lines  
Maximum Output Frequency of 150MHz  
Synchronous Output Enable  
Tristatable Outputs  
32–Lead TQFP Packaging  
FA SUFFIX  
32–LEAD TQFP PACKAGE  
CASE 873A–02  
3.3V V  
Supply Voltage  
CC  
With an output impedance of approximately 7, in both the HIGH and  
LOW logic states, the output buffers of the MPC948 are ideal for driving  
series terminated transmission lines. More specifically, each of the 12  
MPC948 outputs can drive two series terminated 50transmission lines.  
With this capability, the MPC948 has an effective fanout of 1:24 in  
applications where each line drives a single load. With this level of fanout,  
the MPC948 provides enough copies of low skew clocks for high  
performance synchronous systems, including use as a clock distribution  
chip for the L2 cache of a PowerPC 620 based system.  
The differential LVPECL inputs of the MPC948 allow the device to interface directly with a LVPECL fanout buffer like the  
MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input  
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In  
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH  
on the TTL_CLK_Sel pin will select the TTL level clock input.  
All of the control inputs are LVCMOS/LVTTL compatible. The MPC948 provides a synchronous output enable control to allow  
for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control  
is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,  
the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into  
high impedance. Note that all of the MPC948 inputs have internal pullup resistors.  
The MPC948 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and  
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.  
PowerPC is a trademark of International Business Machines Corporation.  
1/97  
REV 3  
Motorola, Inc. 1997  

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