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MPC947FA PDF预览

MPC947FA

更新时间: 2024-11-11 20:57:27
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA PC驱动输出元件逻辑集成电路
页数 文件大小 规格书
8页 95K
描述
Low Skew Clock Driver, LVCMOS/LVTTL Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 0.80 MM PITCH, LQFP-32

MPC947FA 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:7 X 7 MM, 0.80 MM PITCH, LQFP-32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.81
其他特性:WITH SYNCHRONOUS OUTPUT ENABLE; MEETS POWER PC & 620L2 CACHE SKEW REQUIREMENTS系列:LVCMOS/LVTTL
输入调节:MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.02 A
功能数量:1反相输出次数:
端子数量:32实输出次数:9
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
电源:3.3 V传播延迟(tpd):9.25 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.5 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:7 mm最小 fmax:110 MHz
Base Number Matches:1

MPC947FA 数据手册

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Order this document  
by MPC947/D  
SEMICONDUCTOR TECHNICAL DATA  
The MPC947 is a 1:9 low voltage clock distribution chip. The device  
features the capability to select between two LVTTL compatible inputs  
and fans the signal out to 9 LVCMOS or LVTTL compatible outputs.  
These 9 outputs were designed and optimized to drive 50series  
terminated transmission lines. With output–to–output skews of 500ps, the  
MPC947 is ideal as a clock distribution chip for synchronous systems  
which need a tight level of skew at a relatively low cost. For a similar  
product targeted at a higher price/performance point, consult the  
MPC948 data sheet.  
LOW VOLTAGE  
1:9 CLOCK  
DISTRIBUTION CHIP  
2 Selectable LVCMOS/LVTTL Clock Inputs  
500ps Maximum Output–to–Output Skew  
Drives Up to 18 Independent Clock Lines  
Maximum Output Frequency of 110MHz  
Synchronous Output Enable  
Tristatable Outputs  
FA SUFFIX  
32–LEAD LQFP PACKAGE  
CASE 873A–02  
32–Lead LQFP Packaging  
3.3V V  
CC  
Supply Voltage  
With an output impedance of approximately 7, in both the HIGH and  
LOW logic states, the output buffers of the MPC947 are ideal for driving  
series terminated transmission lines. More specifically, each of the 9  
MPC947 outputs can drive two series terminated 50transmission lines.  
With this capability, the MPC947 has an effective fanout of 1:18 in  
applications using point–to–point distribution schemes. With this level of  
fanout, the MPC947 provides enough copies of low skew clocks for high  
performance synchronous systems, including use as a clock distribution  
chip for the L2 cache of a PowerPC 620 based system.  
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to  
provide redundant clock sources or the addition of a test clock into the system design. With the select input pulled HIGH, the  
TTL_CLK1 input will be selected.  
All of the control inputs are LVCMOS/LVTTL compatible. The MPC947 provides a synchronous output enable control to allow  
for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control  
is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,  
the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into  
high impedance. Note that all of the MPC947 inputs have internal pullup resistors.  
The MPC947 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and  
cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.  
06/00  
REV 4  
Motorola, Inc. 2000  

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