Datasheet > MPC948FAR2

MPC948FAR2

更新时间： 2024-11-11 21:22:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		PC 驱动输入元件输出元件逻辑集成电路
页数	文件大小	规格书
4页	90K
描述
LVPECL/LVCMOS/LVTTL SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32

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技术参数
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MPC948FAR2 技术参数

生命周期：	Transferred	包装说明：	LQFP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.71	其他特性：	LVPECL/LVCMOS/LVTTL INPUT TO LVCMOS OUTPUT; MEETS POWER PC & 620L2 CACHE SKEW REQUIREMENTS
系列：	LVPECL/LVCMOS/LVTTL	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQFP-G32	长度：	7 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	12	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
传播延迟（tpd）：	8.9 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.35 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	7 mm
最小 fmax：	150 MHz	Base Number Matches：	1

MPC948FAR2 数据手册

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SEMICONDUCTOR TECHNICAL DATA

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by MPC948/D

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The MPC948 is a 1:12 low voltage clock distribution chip. The device

features the capability to select either a differential LVPECL or a LVTTL

compatible input. The 12 outputs are LVCMOS or LVTTL compatible and

feature the drive strength to drive 50Ω series terminated transmission

lines. With output–to–output skews of 350ps, the MPC948 is ideal as a

clock distribution chip for the most demanding of synchronous systems.

For a similar product targeted at a lower price/performance point, please

consult the MPC947 data sheet.

LOW VOLTAGE

1:12 CLOCK

DISTRIBUTION CHIP

• Clock Distribution for PowerPC 620 L2 Cache

• LVPECL or LVCMOS/LVTTL Clock Input

• 350ps Maximum Output–to–Output Skew

• Drives Up to 24 Independent Clock Lines

• Maximum Output Frequency of 150MHz

• Synchronous Output Enable

• Tristatable Outputs

• 32–Lead LQFP Packaging

• 3.3V V_CCSupply Voltage

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A

With an output impedance of approximately 7Ω, in both the HIGH and

LOW logic states, the output buffers of the MPC948 are ideal for driving

series terminated transmission lines. More specifically, each of the 12

MPC948 outputs can drive two series terminated 50Ω transmission lines.

With this capability, the MPC948 has an effective fanout of 1:24 in ap-

plications where each line drives a single load. With this level of fanout,

the MPC948 provides enough copies of low skew clocks for high perfor-

mance synchronous systems, including use as a clock distribution chip

for the L2 cache of a PowerPC 620 based system.

The differential LVPECL inputs of the MPC948 allow the device to interface directly with a LVPECL fanout buffer like the

MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input

provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In

addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH

on the TTL_CLK_Sel pin will select the TTL level clock input.

All of the control inputs are LVCMOS/LVTTL compatible. The MPC948 provides a synchronous output enable control to allow

for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control

is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,

the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into

high impedance. Note that all of the MPC948 inputs have internal pullup resistors.

The MPC948 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and

cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.

PowerPC is a trademark of International Business Machines Corporation.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

615

12 3 4

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与MPC948FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC948L	MOTOROLA	获取价格	LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP
MPC948LFA	MOTOROLA	获取价格	暂无描述
MPC949	MOTOROLA	获取价格	LOW VOLTAGE 1:15 PECL TO CMOS CLOCK DRIVER
MPC949FA	IDT	获取价格	Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC949FAR2	IDT	获取价格	Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,
MPC949FAR2	MOTOROLA	获取价格	MPC900 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, 10
MPC950	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC950FA	NXP	获取价格	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC
MPC950FA	IDT	获取价格	Processor Specific Clock Generator, 180MHz, CMOS, PQFP32, 7 X 7 MM, LQFP-32
MPC951	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER

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