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MPC946FA PDF预览

MPC946FA

更新时间: 2024-09-23 20:04:31
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
4页 261K
描述
IC,1:10 OUTPUT,CMOS,QFP,32PIN,PLASTIC

MPC946FA 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44系列:946
输入调节:MUXJESD-30 代码:S-PQFP-G32
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:10
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE传播延迟(tpd):12 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.45 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:7 mm最小 fmax:150 MHz
Base Number Matches:1

MPC946FA 数据手册

 浏览型号MPC946FA的Datasheet PDF文件第2页浏览型号MPC946FA的Datasheet PDF文件第3页浏览型号MPC946FA的Datasheet PDF文件第4页 
Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MPC946/D  
ꢄ ꢆꢇ ꢈꢆꢉꢊ ꢋ ꢌ ꢍ ꢎ ꢏꢎ ꢐ ꢑꢀ ꢁꢒ  
ꢑ ꢉꢆꢓ ꢔ ꢕꢖꢗ ꢘꢍ ꢖ  
ꢀꢙ ꢑꢚ ꢛꢜ  
See Upgrade Product – MPC9446  
The MPC946 is a low voltage CMOS, 1:10 clock buffer. The 10 outputs  
can be configured into a standard fanout buffer or into 1X and 1/2X com-  
binations. The ten outputs were designed and optimized to drive 50  
series or parallel terminated transmission lines. With output to output  
skews of 350ps the MPC946 is an ideal clock distribution chip for syn-  
chronous systems which need a tight level of skew from a large number of  
outputs. For a similar product with more outputs consult the MPC949 data  
sheet.  
LOW VOLTAGE  
1:10 CMOS CLOCK DRIVER  
2 Selectable LVCMOS/LVTTL Clock Inputs  
350ps Output to Output Skew  
Drives up to 20 Series Terminated Independent Clock Lines  
Maximum Input/Output Frequency of 150MHz  
Tristatable Outputs  
32–Lead LQFP Packaging  
3.3V VCC Supply  
With an output impedance of approximately 7, in both the HIGH and  
the LOW logic states, the output buffers of the MPC946 are ideal for driv-  
ing series terminated transmission lines. More specifically each of the 10  
MPC946 outputs can drive two series terminated transmission lines. With  
this capability, the MPC946 has an effective fanout of 1:20 in applications  
using point–to–point distribution schemes.  
FA SUFFIX  
LQFP PACKAGE  
CASE 873A  
The MPC946 has the capability of generating 1X and 1/2X signals from  
a 1X source. The design is fully static, the signals are generated and  
retimed inside the chip to ensure minimal skew between the 1X and 1/2X  
signals. The device features selectability to allow the user to select the  
ratio of 1X outputs to 1/2X outputs.  
6
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to  
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the  
TCLK1 input is selected.  
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the  
Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced  
HIGH.  
The MPC946 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and  
cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.  
Rev 2  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
607  
For More Information On This Product,  
Go to: www.freescale.com  

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