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MPC9449FAR2 PDF预览

MPC9449FAR2

更新时间: 2024-11-11 21:03:19
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
8页 310K
描述
Low Skew Clock Driver, 9449 Series, 15 True Output(s), 0 Inverted Output(s), ECL, PQFP52, PLASTIC, LQFP-52

MPC9449FAR2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, LQFP-52针数:52
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.21
其他特性:ALSO OPERATE AT 3.3V SUPPLY系列:9449
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G52
JESD-609代码:e0长度:10 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.024 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:52
实输出次数:15最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP52,.47SQ封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
电源:2.5/3.3 VProp。Delay @ Nom-Sup:7 ns
传播延迟(tpd):7 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.3 ns座面最大高度:1.7 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

MPC9449FAR2 数据手册

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ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ  
SEMICONDUCTOR TECHNICAL DATA  
Order Number: MPC9449/D  
Rev 1, 08/2002  
Freescale Semiconductor, Inc.  
ꢆꢇꢆꢈꢉꢊꢇ ꢋꢈ ꢌ ꢍꢌ ꢋ ꢎꢏ ꢐ ꢄꢉꢐꢀꢁ ꢑ  
ꢐ ꢒꢓꢔ ꢕ ꢖ ꢗ ꢘ ꢓꢙ ꢚ ꢛ ꢙ ꢜꢜ ꢝ ꢞ  
The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer  
targeted for high performance clock tree applications. With output fre-  
quencies up to 200 MHz and output skews less than 200 ps the device  
meets the needs of the most demanding clock applications.  
3.3V/2.5V 1:15  
PECL/LVCMOS  
CLOCK FANOUT BUFFER  
Features  
15 LVCMOS compatible clock outputs  
Two selectable LVCMOS and one differential LVPECL compatible clock  
inputs  
Selectable output frequency divider (divide-by-one and divide-by-two)  
Maximum clock frequency of 200 MHz  
Maximum clock skew of 200 ps  
High-impedance output control  
3.3V or 2.5V power supply  
Drives up to 30 series terminated clock lines  
Ambient temperature range –40°C to +85°C  
52 lead LQFP packaging  
Supports clock distribution in networking, telecommunication and com-  
FA SUFFIX  
52 LEAD LQFP PACKAGE  
CASE 848D  
puting applications  
Pin and function compatible to MPC949  
Functional Description  
The MPC9449 is specifically designed to distribute LVCMOS compat-  
ible clock signals up to a frequency of 200 MHz. The device has 15 identi-  
cal outputs, organized in 4 output banks. Each output bank provides a  
retimed or frequency divided copy of the input signal with a near zero  
skew. The output buffer supports driving of 50terminated transmission  
lines on the incident edge: each output is capable of driving either one  
parallel terminated or two series terminated transmission lines.  
6
Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In  
addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input refer-  
ence frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the OE  
control will force the outputs into high-impedance mode.  
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports  
a 2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9449 is pin and function compatible  
but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
591  
For More Information On This Product,  
Go to: www.freescale.com  

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