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MPC9456FAR2 PDF预览

MPC9456FAR2

更新时间: 2024-09-23 14:53:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
8页 303K
描述
Low Skew Clock Driver, 9456 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, PLASTIC, LQFP-32

MPC9456FAR2 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, PLASTIC, LQFP-32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.26
Is Samacsys:N其他特性:ALSO OPERATE AT 3.3V SUPPLY
系列:9456输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.015 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:2.5/3.3 V
传播延迟(tpd):5.6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.35 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mmBase Number Matches:1

MPC9456FAR2 数据手册

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ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ  
SEMICONDUCTOR TECHNICAL DATA  
Order Number: MPC9456/D  
Rev 1, 03/2002  
Freescale Semiconductor, Inc.  
ꢍ ꢇꢍ ꢉ ꢎꢀꢁ ꢏ ꢎꢐ ꢑꢒ ꢓ  
ꢕ ꢘꢘ ꢙ ꢚ  
The MPC9456 is a 2.5V and 3.3V compatible 1:10 clock distribution  
buffer designed for low-voltage mid-range to high-performance telecom,  
networking and computing applications. Both 3.3V, 2.5V and dual supply  
voltages are supported for mixed-voltage applications. The MPC9456 of-  
fers 10 low-skew outputs and a differential LVPECL clock input. The out-  
puts are configurable and support 1:1 and 1:2 output to input frequency  
ratios. The MPC9456 is specified for the extended temperature range of  
–40 to 85°C.  
LOW VOLTAGE SINGLE OR  
DUAL SUPPLY 2.5V AND 3.3V  
LVCMOS CLOCK  
DISTRIBUTION BUFFER  
Features  
Configurable 10 outputs LVCMOS clock distribution buffer  
Compatible to single, dual and mixed 3.3V/2.5V voltage supply  
Wide range output clock frequency up to 250 MHz  
Designed for mid-range to high-performance telecom, networking and  
computer applications  
Supports high-performance differential clocking applications  
Max. output skew of 200 ps (150 ps within one bank)  
Selectable output configurations per output bank  
Tristable outputs  
32 ld LQFP package  
Ambient operating temperature range of –40 to 85°C  
FA SUFFIX  
LQFP PACKAGE  
CASE 873A  
Functional Description  
The MPC9456 is a full static design supporting clock frequencies up to  
250 MHz. The signals are generated and retimed on-chip to ensure mini-  
mal skew between the three output banks.  
6
Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx  
pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for  
each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic  
high state). Asserting MR/OE will enable the outputs.  
All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive  
terminated 50 transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support.  
Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of  
the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7  
mm2 32-lead LQFP package.  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
599  
For More Information On This Product,  
Go to: www.freescale.com  

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