Datasheet > MPC9456

MPC9456

更新时间： 2024-09-23 10:49:15

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		时钟
页数	文件大小	规格书
12页	285K
描述
2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER

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MPC9456 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9456/D

Rev 1, 03/2002

The MPC9456 is a 2.5V and 3.3V compatible 1:10 clock distribution

buffer designed for low-voltage mid-range to high-performance telecom,

networking and computing applications. Both 3.3V, 2.5V and dual supply

voltages are supported for mixed-voltage applications. The MPC9456

offers 10 low-skew outputs and a differential LVPECL clock input. The

outputs are configurable and support 1:1 and 1:2 output to input

frequency ratios. The MPC9456 is specified for the extended temperature

range of –40 to 85°C.

LOW VOLTAGE SINGLE OR

DUAL SUPPLY 2.5V AND 3.3V

LVCMOS CLOCK

DISTRIBUTION BUFFER

Features

• Configurable 10 outputs LVCMOS clock distribution buffer

• Compatible to single, dual and mixed 3.3V/2.5V voltage supply

• Wide range output clock frequency up to 250 MHz

• Designed for mid-range to high-performance telecom, networking and

computer applications

• Supports high-performance differential clocking applications

• Max. output skew of 200 ps (150 ps within one bank)

• Selectable output configurations per output bank

• Tristable outputs

FA SUFFIX

LQFP PACKAGE

CASE 873A–02

• 32 ld LQFP package

• Ambient operating temperature range of –40 to 85°C

Functional Description

The MPC9456 is a full static design supporting clock frequencies up to

250 MHz. The signals are generated and retimed on-chip to ensure

minimal skew between the three output banks.

Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx

pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for

each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic

high state). Asserting MR/OE will enable the outputs.

All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive

terminated 50 Ω transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support.

Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of

the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7

mm 32-lead LQFP package.

For More Information On This Product,

Motorola, Inc. 2002

Go to: www.freescale.com

12 3 4 5 6 7...12

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与MPC9456相关器件

型号	品牌	获取价格	描述	数据表
MPC9456AC	NXP	获取价格	9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9456ACR2	NXP	获取价格	9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9456FA	MOTOROLA	获取价格	LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC9456FA	NXP	获取价格	IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC
MPC9456FA	FREESCALE	获取价格	2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER
MPC9456FAR2	NXP	获取价格	9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9456FAR2	MOTOROLA	获取价格	Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, PLASTIC,
MPC9456FAR2	IDT	获取价格	Low Skew Clock Driver, 9456 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC946	MOTOROLA	获取价格	LOW VOLTAGE 1:10 CMOS CLOCK DRIVER
MPC946FA	NXP	获取价格	IC,1:10 OUTPUT,CMOS,QFP,32PIN,PLASTIC

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