Datasheet > MPC947

MPC947

更新时间： 2024-09-22 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
6页	101K
描述
LOW VOLTAGE 1:9 CLOCK DISTRIBUTION CHIP

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数据手册

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MPC947 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC947 is a 1:9 low voltage clock distribution chip. The device

features the capability to select between two LVTTL compatible inputs

and fans the signal out to 9 LVCMOS or LVTTL compatible outputs.

These 9 outputs were designed and optimized to drive 50Ω series

terminated transmission lines. With output–to–output skews of 500ps, the

MPC947 is ideal as a clock distribution chip for synchronous systems

which need a tight level of skew at a relatively low cost. For a similar

product targeted at a higher price/performance point, consult the

MPC948 data sheet.

LOW VOLTAGE

1:9 CLOCK

DISTRIBUTION CHIP

• Clock Distribution for PowerPC 620 L2 Cache

• 2 Selectable LVCMOS/LVTTL Clock Inputs

• 500ps Maximum Output–to–Output Skew

• Drives Up to 18 Independent Clock Lines

• Maximum Output Frequency of 110MHz

• Synchronous Output Enable

• Tristatable Outputs

• 32–Lead TQFP Packaging

FA SUFFIX

32–LEAD TQFP PACKAGE

CASE 873A–02

• 3.3V V

Supply Voltage

With an output impedance of approximately 7Ω, in both the HIGH and

LOW logic states, the output buffers of the MPC947 are ideal for driving

series terminated transmission lines. More specifically, each of the 9

MPC947 outputs can drive two series terminated 50Ω transmission lines.

With this capability, the MPC947 has an effective fanout of 1:18 in

applications using point–to–point distribution schemes. With this level of

fanout, the MPC947 provides enough copies of low skew clocks for high

performance synchronous systems, including use as a clock distribution

chip for the L2 cache of a PowerPC 620 based system.

Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to

provide redundant clock sources or the addition of a test clock into the system design. With the select input pulled HIGH, the

TTL_CLK1 input will be selected.

All of the control inputs are LVCMOS/LVTTL compatible. The MPC947 provides a synchronous output enable control to allow

for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control

is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,

the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into

high impedance. Note that all of the MPC947 inputs have internal pullup resistors.

The MPC947 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and

cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.

PowerPC is a trademark of International Business Machines Corporation.

1/97

REV 3

Motorola, Inc. 1997

12 3 4 5 6

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与MPC947相关器件

型号	品牌	获取价格	描述	数据表
MPC947FA	MOTOROLA	获取价格	Low Skew Clock Driver, LVCMOS/LVTTL Series, 9 True Output(s), 0 Inverted Output(s), CMOS,
MPC947FAR2	NXP	获取价格	947 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 M
MPC948	MOTOROLA	获取价格	LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP
MPC948FA	MOTOROLA	获取价格	LVPECL/LVCMOS/LVTTL SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S)
MPC948FAR2	IDT	获取价格	Low Skew Clock Driver, 948 Series, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC948FAR2	MOTOROLA	获取价格	LVPECL/LVCMOS/LVTTL SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S)
MPC948L	MOTOROLA	获取价格	LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP
MPC948LFA	MOTOROLA	获取价格	暂无描述
MPC949	MOTOROLA	获取价格	LOW VOLTAGE 1:15 PECL TO CMOS CLOCK DRIVER
MPC949FA	IDT	获取价格	Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52,

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