Datasheet > MPC9449FAR2

MPC9449FAR2

更新时间： 2024-09-23 14:53:55

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		驱动输出元件逻辑集成电路
页数	文件大小	规格书
8页	132K
描述
LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52

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MPC9449FAR2 技术参数

生命周期：	Transferred	包装说明：	LQFP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.71	其他特性：	CAN ALSO OPERATE WITH 3.3V SUPPLY
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-PQFP-G52
长度：	10 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	52	实输出次数：	15
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	传播延迟（tpd）：	7 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.3 ns
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	10 mm
Base Number Matches：	1

MPC9449FAR2 数据手册

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9449/D

Rev 1, 08/2002

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The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer

targeted for high performance clock tree applications. With output fre-

quencies up to 200 MHz and output skews less than 200 ps the device

meets the needs of the most demanding clock applications.

3.3V/2.5V 1:15

PECL/LVCMOS

CLOCK FANOUT BUFFER

Features

• 15 LVCMOS compatible clock outputs

• Two selectable LVCMOS and one differential LVPECL compatible clock

inputs

• Selectable output frequency divider (divide-by-one and divide-by-two)

• Maximum clock frequency of 200 MHz

• Maximum clock skew of 200 ps

• High-impedance output control

• 3.3V or 2.5V power supply

• Drives up to 30 series terminated clock lines

• Ambient temperature range –40°C to +85°C

• 52 lead LQFP packaging

• Supports clock distribution in networking, telecommunication and com-

FA SUFFIX

52 LEAD LQFP PACKAGE

CASE 848D

puting applications

• Pin and function compatible to MPC949

Functional Description

The MPC9449 is specifically designed to distribute LVCMOS compat-

ible clock signals up to a frequency of 200 MHz. The device has 15 identi-

cal outputs, organized in 4 output banks. Each output bank provides a

retimed or frequency divided copy of the input signal with a near zero

skew. The output buffer supports driving of 50Ω terminated transmission

lines on the incident edge: each output is capable of driving either one

parallel terminated or two series terminated transmission lines.

Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In

addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input refer-

ence frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the OE

control will force the outputs into high-impedance mode.

All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports

a 2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9449 is pin and function compatible

but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

591

12 3 4 5 6 7 8

中文翻译

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与MPC9449FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC94551	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC94551D	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC94551DR2	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC94551EF	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC94551EFR2	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC9456	FREESCALE	获取价格	2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER
MPC9456AC	NXP	获取价格	9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9456ACR2	NXP	获取价格	9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9456FA	MOTOROLA	获取价格	LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC9456FA	NXP	获取价格	IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC

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