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MPC9448FAR2 PDF预览

MPC9448FAR2

更新时间: 2024-11-11 14:19:51
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
10页 395K
描述
Clock Driver

MPC9448FAR2 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, LQFP-32针数:32
Reach Compliance Code:not_compliant风险等级:5.24
Is Samacsys:NBase Number Matches:1

MPC9448FAR2 数据手册

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ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ  
SEMICONDUCTOR TECHNICAL DATA  
Order Number: MPC9448/D  
Rev 3, 04/2003  
Freescale Semiconductor, Inc.  
ꢇꢆꢈꢉꢊꢇ ꢋꢈ ꢌꢀꢁ ꢍ ꢎ ꢏꢎ ꢊ ꢌꢐ ꢑꢒ ꢓ  
ꢕ ꢖ ꢑꢗ ꢘ ꢙꢗ ꢚꢚ ꢛ ꢜ  
The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer  
targeted for high performance clock tree applications. With output fre-  
quencies up to 350 MHz and output skews less than 150 ps, the device  
meets the needs of most demanding clock applications.  
LOW VOLTAGE  
3.3V/2.5V LVCMOS 1:12  
CLOCK FANOUT BUFFER  
12 LVCMOS compatible clock outputs  
Selectable LVCMOS and differential LVPECL compatible clock inputs  
Maximum clock frequency of 350 MHz  
Maximum clock skew of 150 ps  
Synchronous output stop in logic low state eliminates output runt pulses  
High–impedance output control  
3.3V or 2.5V power supply  
Drives up to 24 series terminated clock lines  
Ambient temperature range –40°C to +85°C  
32–Lead LQFP packaging  
Supports clock distribution in networking, telecommunication and com-  
puting applications  
FA SUFFIX  
32–LEAD LQFP PACKAGE  
CASE 873A  
Pin and function compatible to MPC948  
Functional Description  
The MPC9448 is specifically designed to distribute LVCMOS compat-  
ible clock signals up to a frequency of 350 MHz. Each output provides a  
precise copy of the input signal with a near zero skew. The outputs buff-  
ers support driving of 50terminated transmission lines on the incident  
edge: each output is capable of driving either one parallel terminated or  
two series terminated transmission lines.  
6
Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribu-  
tion systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop  
of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force  
the outputs into high–impedance mode.  
All inputs have an internal pull–up or pull–down resistor preventing unused and open inputs from floating. The device supports  
a 2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9448 is pin and function compatible  
but performance–enhanced to the MPC948.  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
581  
For More Information On This Product,  
Go to: www.freescale.com  

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