MPC9449

更新时间： 2024-09-23 12:28:15

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
11页	358K
描述
3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer High-impedance output control

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MPC9449 数据手册

3.3 V/2.5 V 1:15 PECL/LVCMOS Clock

Fanout Buffer

MPC9449

NRND

DATASHEET

NRND – Not Recommend for New Designs

The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted

for high performance clock tree applications. With output frequencies up to

200 MHz and output skews less than 200 ps the device meets the needs of the

most demanding clock applications.

Features

•

15 LVCMOS compatible clock outputs

3.5 V/2.5 V 1:15

PECL/LVCMOS

Two selectable LVCMOS and one differential LVPECL compatible clock

inputs

CLOCK FANOUT BUFFER

•

Selectable output frequency divider (divide-by-one and divide-by-two)

Maximum clock frequency of 200 MHz

Maximum clock skew of 200 ps

High-impedance output control

3.3 V or 2.5 V power supply

Drives up to 30 series terminated clock lines

Ambient temperature range –40C to +85C

52-lead LQFP packaging, Pb-free

AE SUFFIX

52-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 848D-03

Supports clock distribution in networking, telecommunication and computing

applications

•

Pin and function compatible to MPC949

Functional Description

The MPC9449 is specifically designed to distribute LVCMOS compatible clock

signals up to a frequency of 200 MHz. The device has 15 identical outputs,

organized in four output banks. Each output bank provides a retimed or

frequency divided copy of the input signal with a near zero skew. The output

buffer supports driving of 50  terminated transmission lines on the incident

edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines.

Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In

addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input

reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the

OE control will force the outputs into high-impedance mode.

All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports

a 2.5 V or 3.3 V power supply and an ambient temperature range of –40C to +85C. The MPC9449 is pin and function

compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.

MPC9449 REVISION 6 DECEMBER 21, 2012

12 3 4 5 6 7...11

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与MPC9449相关器件

型号	品牌	获取价格	描述	数据表
MPC9449AER2	IDT	获取价格	9449 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLAST
MPC9449FA	IDT	获取价格	Low Skew Clock Driver, 9449 Series, 15 True Output(s), 0 Inverted Output(s), ECL, PQFP52,
MPC9449FA	MOTOROLA	获取价格	Low Skew Clock Driver, 15 True Output(s), 0 Inverted Output(s), ECL, PQFP52, PLASTIC, LQFP
MPC9449FAR2	IDT	获取价格	Low Skew Clock Driver, 9449 Series, 15 True Output(s), 0 Inverted Output(s), ECL, PQFP52,
MPC9449FAR2	MOTOROLA	获取价格	LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52
MPC94551	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC94551D	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC94551DR2	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC94551EF	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer
MPC94551EFR2	FREESCALE	获取价格	Low Voltage 1:4 CMOS Clock Buffer

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