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MPC9446ACR2 PDF预览

MPC9446ACR2

更新时间: 2024-10-01 20:02:55
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
8页 244K
描述
9446 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32

MPC9446ACR2 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFP包装说明:7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32
针数:32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.25
Is Samacsys:N其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:9446输入调节:MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.015 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
传播延迟(tpd):5.6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.35 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mmBase Number Matches:1

MPC9446ACR2 数据手册

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Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MPC946/D  
The MPC946 is a low voltage CMOS, 1:10 clock buffer. The 10 outputs  
can be configured into a standard fanout buffer or into 1X and 1/2X  
combinations. The ten outputs were designed and optimized to drive 50  
series or parallel terminated transmission lines. With output to output  
skews of 350ps the MPC946 is an ideal clock distribution chip for  
synchronous systems which need a tight level of skew from a large  
number of outputs. For a similar product with more outputs consult the  
MPC949 data sheet.  
LOW VOLTAGE  
1:10 CMOS CLOCK DRIVER  
2 Selectable LVCMOS/LVTTL Clock Inputs  
350ps Output to Output Skew  
Drives up to 20 Series Terminated Independent Clock Lines  
Maximum Input/Output Frequency of 150MHz  
Tristatable Outputs  
32–Lead LQFP Packaging  
3.3V VCC Supply  
With an output impedance of approximately 7, in both the HIGH and  
the LOW logic states, the output buffers of the MPC946 are ideal for  
driving series terminated transmission lines. More specifically each of the  
10 MPC946 outputs can drive two series terminated transmission lines.  
With this capability, the MPC946 has an effective fanout of 1:20 in  
applications using point–to–point distribution schemes.  
FA SUFFIX  
LQFP PACKAGE  
CASE 873A–02  
The MPC946 has the capability of generating 1X and 1/2X signals from  
a 1X source. The design is fully static, the signals are generated and  
retimed inside the chip to ensure minimal skew between the 1X and 1/2X  
signals. The device features selectability to allow the user to select the  
ratio of 1X outputs to 1/2X outputs.  
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to  
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the  
TCLK1 input is selected.  
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the  
Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced  
HIGH.  
The MPC946 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and  
cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.  
06/00  
For More Information On This Product,  
Go to: www.freescale.cRoEmV 2  
Motorola, Inc. 2000  

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