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MPC9448FA PDF预览

MPC9448FA

更新时间: 2024-09-23 19:48:39
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动逻辑集成电路
页数 文件大小 规格书
12页 160K
描述
Low Skew Clock Driver, 12 True Output(s), 0 Inverted Output(s), ECL, PQFP32, PLASTIC, LQFP-32

MPC9448FA 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:PLASTIC, LQFP-32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.81
其他特性:CAN ALSO OPERATE WITH 3.3V SUPPLY输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:12最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
传播延迟(tpd):4.4 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:7 mm最小 fmax:350 MHz
Base Number Matches:1

MPC9448FA 数据手册

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Order Number: MPC9448/D  
Rev 3, 04/2003  
SEMICONDUCTOR TECHNICAL DATA  
The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer  
targeted for high performance clock tree applications. With output  
frequencies up to 350 MHz and output skews less than 150 ps, the device  
meets the needs of most demanding clock applications.  
LOW VOLTAGE  
3.3V/2.5V LVCMOS 1:12  
CLOCK FANOUT BUFFER  
12 LVCMOS compatible clock outputs  
Selectable LVCMOS and differential LVPECL compatible clock inputs  
Maximum clock frequency of 350 MHz  
Maximum clock skew of 150 ps  
Synchronous output stop in logic low state eliminates output runt pulses  
High–impedance output control  
3.3V or 2.5V power supply  
Drives up to 24 series terminated clock lines  
Ambient temperature range –40°C to +85°C  
32–Lead LQFP packaging  
FA SUFFIX  
32–LEAD LQFP PACKAGE  
CASE 873A  
Supports clock distribution in networking, telecommunication and  
computing applications  
Pin and function compatible to MPC948  
Functional Description  
The MPC9448 is specifically designed to distribute LVCMOS  
compatible clock signals up to a frequency of 350 MHz. Each output  
provides a precise copy of the input signal with a near zero skew. The  
outputs buffers support driving of 50terminated transmission lines on  
the incident edge: each output is capable of driving either one parallel  
terminated or two series terminated transmission lines.  
Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock  
distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start  
and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control  
will force the outputs into high–impedance mode.  
All inputs have an internal pull–up or pull–down resistor preventing unused and open inputs from floating. The device supports  
a 2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9448 is pin and function compatible  
but performance–enhanced to the MPC948.  
Motorola, Inc. 2003  

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