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MPC9448AC PDF预览

MPC9448AC

更新时间： 2024-11-20 20:08:27
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
12页 180K
描述
9448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, LQFP-32

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MPC9448AC 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：QFP包装说明：LEAD FREE, LQFP-32
针数：32Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.21
其他特性：ALSO OPERATES AT 3.3V SUPPLY系列：9448
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQFP-G32
JESD-609代码：e3长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：32实输出次数：12
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：260
传播延迟（tpd）：4.4 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.15 ns座面最大高度：1.6 mm
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：TIN
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：7 mm最小 fmax：350 MHz
Base Number Matches：1

MPC9448AC 数据手册

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Document Number: MPC9448  
Rev. 5, 1/2005  
Freescale Semiconductor  
Technical Data  
3.3 V/2.5 V LVCMOS 1:12 Clock  
Fanout Buffer  
MPC9448  
The Freescale Semiconductor, Inc. MPC9448 is a 3.3 V or 2.5 V compatible,  
1:12 clock fanout buffer targeted for high performance clock tree applications.  
With output frequencies up to 350 MHz and output skews less than 150 ps, the  
device meets the needs of most demanding clock applications.  
LOW VOLTAGE  
3.3 V/2.5 V LVCMOS 1:12  
CLOCK FANOUT BUFFER  
Features  
•
•
•
•
•
•
•
•
•
•
•
•
12 LVCMOS compatible clock outputs  
Selectable LVCMOS and differential LVPECL compatible clock inputs  
Maximum clock frequency of 350 MHz  
Maximum clock skew of 150 ps  
Synchronous output stop in logic low state eliminates output runt pulses  
High-impedance output control  
FA SUFFIX  
32-LEAD LQFP PACKAGE  
CASE 873A-03  
3.3 V or 2.5 V power supply  
Drives up to 24 series terminated clock lines  
Ambient temperature range -40°C to +85°C  
32-Lead LQFP packaging  
32-lead Pb-free package available  
AC SUFFIX  
32-LEAD LQFP PACKAGE  
Pb-FREE PACKAGE  
CASE 873A-03  
Supports clock distribution in networking, telecommunication and computing  
applications  
•
Pin and function compatible to MPC948  
Functional Description  
The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each  
output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50 Ω terminated  
transmission lines on the incident edge. Each output is capable of driving either one parallel terminated or two series terminated  
transmission lines.  
Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribu-  
tion systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop  
of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force  
the outputs into high-impedance mode.  
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports  
a 2.5 V or 3.3 V power supply and an ambient temperature range of -40°C to +85°C. The MPC9448 is pin and function compatible  
but performance-enhanced to the MPC948.  
© Freescale Semiconductor, Inc., 2005. All rights reserved.  
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MPC9448FAR2 MOTOROLA

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