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MPC941FAR2 PDF预览

MPC941FAR2

更新时间: 2024-10-01 14:53:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA PC驱动输出元件逻辑集成电路
页数 文件大小 规格书
9页 145K
描述
MPC900 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, PLASTIC, LQFP-48

MPC941FAR2 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP,针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.27其他特性:CAN ALSO OPERATE AT 3.3V SUPPLY
系列:MPC900输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G48长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:48
实输出次数:27最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
传播延迟(tpd):2.9 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.6 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:7 mm最小 fmax:250 MHz
Base Number Matches:1

MPC941FAR2 数据手册

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ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MPC941/D  
ꢄ ꢆꢇ ꢈꢆꢉꢊ ꢋ ꢌ ꢍ ꢎ ꢏꢐ ꢑ ꢒꢉꢆꢓ ꢔ  
ꢕꢖ ꢗꢊ ꢘꢖꢙ ꢚ ꢊꢖꢆꢛ ꢒꢜ ꢖꢝ  
The MPC941 is a 1:27 low voltage clock distribution chip. The device  
features the capability to select either a differential LVPECL or an  
LVCMOS compatible input. The 27 outputs are LVCMOS compatible and  
feature the drive strength to drive 50series or parallel terminated trans-  
mission lines. With output–to–output skews of 250ps, the MPC941 is  
ideal as a clock distribution chip for the most demanding of synchronous  
systems. For a similar product with a smaller number of outputs, please  
consult the MPC940 data sheet.  
LOW VOLTAGE 3.3V/2.5V  
1:27 CLOCK  
DISTRIBUTION CHIP  
LVPECL or LVCMOS Clock Input  
250ps Maximum Output–to–Output Skew  
Drives Up to 54 Independent Clock Lines  
Maximum Output Frequency of 250MHz  
High Impedance Output Enable  
Extended Temperature Range: –40°C to +85°C  
48–Lead LQFP Packaging  
3.3V or 2.5V VCC Supply Voltage  
With a low output impedance, in both the HIGH and LOW logic states,  
the output buffers of the MPC941 are ideal for driving series terminated  
transmission lines. More specifically, each of the 27 MPC941 outputs can  
drive two series terminated 50transmission lines. With this capability,  
the MPC941 has an effective fanout of 1:54. With this level of fanout, the  
MPC941 provides enough copies of low skew clocks for most high perfor-  
mance synchronous systems.  
FA SUFFIX  
48–LEAD LQFP PACKAGE  
CASE 932  
6
The differential LVPECL inputs of the MPC941 allow the device to interface directly with an LVPECL fanout buffer like the  
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a  
more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the  
two clock sources can be used as a test clock interface as well as the primary system clock. A logic HIGH on the  
LVCMOS_CLK_Sel pin will select the LVCMOS level clock input.  
The MPC941 is fully 3.3V and 2.5V compatible. The 48–lead LQFP package was chosen to optimize performance, board  
space and cost of the device. The 48–lead LQFP has a 7x7mm body size.  
Rev 4  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
539  

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