Datasheet > MPC93R51FA

MPC93R51FA

更新时间： 2024-11-04 18:20:51

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件逻辑集成电路
页数	文件大小	规格书
12页	339K
描述
93R SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32

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MPC93R51FA 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	7 X 7 MM, LQFP-32
针数：	32	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.27
系列：	93R	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.024 A	湿度敏感等级：	2
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	9
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP32,.35SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	220	电源：	3.3 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.15 ns
座面最大高度：	1.6 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	7 mm
最小 fmax：	100 MHz	Base Number Matches：	1

MPC93R51FA 数据手册

MPC93R51

Rev. 4, 1/2005

Freescale Semiconductor

Technical Data

Low Voltage PLL Clock Driver

MPC93R51

The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for

high performance clock distribution systems. With output frequencies of up to

240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal

solution for the most demanding clock tree designs. The device offers 9 low skew

clock outputs, each is configurable to support the clocking needs of the various

high-performance microprocessors including the PowerQuicc II integrated

communication microprocessor. The devices employ a fully differential PLL

design to minimize cycle-to-cycle and long-term jitter.

LOW VOLTAGE 3.3 V

PLL CLOCK GENERATOR

Features

•

9 outputs LVCMOS PLL clock generator

25–240 MHz output frequency range

Fully integrated PLL

Compatible to various microprocessors such as PowerQuicc II

Supports networking, telecommunications and computer applications

Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

LVPECL and LVCMOS compatible inputs

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

External feedback enables zero-delay configurations

Output enable/disable and static test mode (PLL enable/disable)

Low skew characteristics: maximum 150 ps output-to-output

Cycle-to-cycle jitter max. 22 ps RMS

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

32-lead LQFP package

32-lead Pb-free Package Available

Ambient Temperature Range 0°C to +70°C

Pin & Function Compatible with the MPC951

Functional Description

The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal

operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback

path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be

selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of

the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs

is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using

the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2

and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input

(TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test

mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended

for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification

does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes

the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase

locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3 V compatible and requires no external

loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible

levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the

MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a

7x7 mm²32-lead LQFP package.

Application Information

The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with

essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase

offset between the outputs and the reference signal.

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Freescale Confidential Proprietary, NDA Required / Preliminary

12 3 4 5 6 7...12

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与MPC93R51FA相关器件

型号	品牌	获取价格	描述	数据表
MPC93R51FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC93R52	MOTOROLA	获取价格	LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR
MPC93R52ACR2	NXP	获取价格	93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD
MPC93R52FA	MOTOROLA	获取价格	PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, PLASTIC, LQ
MPC93R52FAR2	IDT	获取价格	PLL Based Clock Driver, 93R Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLAST
MPC93R52FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32
MPC940	MOTOROLA	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940L	MOTOROLA	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940L	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940LAC	IDT	获取价格	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP

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