Datasheet > MPC93R52FAR2

MPC93R52FAR2

更新时间： 2024-01-17 19:41:54

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
11页	345K
描述
PLL Based Clock Driver, 93R Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32

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MPC93R52FAR2 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	零件包装代码：	QFP
包装说明：	LQFP, QFP32,.35SQ,32	针数：	32
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.39	其他特性：	ALSO OPERATE AT 3.3V SUPPLY
系列：	93R	输入调节：	STANDARD
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.024 A	湿度敏感等级：	2
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	11
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP32,.35SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	220	电源：	3.3 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.15 ns
座面最大高度：	1.6 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	7 mm	最小 fmax：	100 MHz

MPC93R52FAR2 数据手册

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC93R52/D

Rev 2, 04/2003

Freescale Semiconductor, Inc.

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The MPC93R52 is a 3.3V compatible, 1:11 PLL based clock generator

targeted for high performance clock tree applications. With output fre-

quencies up to 240 MHz and output skews lower than 200 ps the device

meets the needs of most demanding clock applications.

LOW VOLTAGE

3.3V LVCMOS 1:11

CLOCK GENERATOR

Features

• Configurable 11 outputs LVCMOS PLL clock generator

• Fully integrated PLL

• Wide range of output clock frequency of 16.67 MHz to 240 MHz

• Multiplication of the input reference clock frequency by 3, 2, 1, 3B2,

2B3, 1B3 and 1B2

• 3.3V LVCMOS compatible

• Maximum output skew of 200 ps

• Supports zero–delay applications

• Designed for high–performance telecom, networking and computing

applications

• 32 lead LQFP package

• Ambient Temperature Range – 0°C to +70°C

• Pin and function compatible to the MPC952

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

Functional Description

The MPC93R52 is a fully 3.3V compatible PLL clock generator and

clock driver. The device has the capability to generate output clock sig-

nals of 16.67 to 240 MHz from external clock sources. The internal PLL

optimized for its frequency range and does not require external look filter

components. One output of the MPC93R52 has to be connected to the

PLL feedback input FB_IN to close the external PLL feedback path. The

output divider of this output setting determines the PLL frequency multi-

plication factor. This multiplication factor, F_RANGE and the reference

clock frequency must be selected to situate the VCO in its specified lock

range. The frequency of the clock outputs can be configured individually

for all three output banks by the FSELx pins supporting systems with

different but phase-aligned clock frequencies.

The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and

outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50Ω transmission lines. Alternatively,

each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.

The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The

MPC93R52 is package in a 32 ld LQFP.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

139

For More Information On This Product,

Go to: www.freescale.com

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与MPC93R52FAR2相关器件

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