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MPC93H52FA PDF预览

MPC93H52FA

更新时间: 2024-11-04 20:57:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动逻辑集成电路
页数 文件大小 规格书
16页 471K
描述
PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, LQFP-32

MPC93H52FA 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.38输入调节:STANDARD
JESD-30 代码:S-PQFP-G32长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.024 A
功能数量:1反相输出次数:
端子数量:32实输出次数:11
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.3 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:7 mm最小 fmax:100 MHz
Base Number Matches:1

MPC93H52FA 数据手册

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Freescale Semiconductor, Inc.  
MOTOROLA  
Order number: MPC93H52/D  
Rev 2, 2/2004  
SEMICONDUCTOR TECHNICAL DATA  
MPC93H52  
3.3V 1:11 LVCMOS Zero Delay  
Clock Generator  
The MPC93H52 is a 3.3V compatible, 1:11 PLL based clock gener-  
ator targeted for high performance clock tree applications. With output  
frequencies up to 240 MHz and output skews lower than 200 ps the  
device meets the needs of most demanding clock applications.  
LOW VOLTAGE  
3.3V LVCMOS 1:11  
CLOCK GENERATOR  
Features  
Configurable 11 outputs LVCMOS PLL clock generator  
Fully integrated PLL  
Wide range of output clock frequency of 16.67 MHz to 240 MHz  
Multiplication of the input reference clock frequency by 3, 2, 1, 3÷2,  
2÷3, 1÷3 and 1÷2  
FA SUFFIX  
32-LEAD LQFP PACKAGE  
CASE 873A-03  
3.3V LVCMOS compatible  
Maximum output skew of 200 ps  
Supports zero-delay applications  
Designed for high-performance telecom, networking and  
computing applications  
32 lead LQFP package  
Ambient Temperature Range — 0°C to +70°C  
Pin and function compatible to the MPC952  
Functional Description  
The MPC93H52 is a fully 3.3V compatible PLL clock generator and clock driver. The device has the capability to gen-  
erate output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL optimized for its frequency  
range and does not require external look filter components. One output of the MPC93H52 has to be connected to the  
PLL feedback input FB_IN to close the external PLL feedback path. The output divider of this output setting determines  
the PLL frequency multiplication factor. This multiplication factor, F_RANGE and the reference clock frequency must be  
selected to situate the VCO in its specified lock range. The frequency of the clock outputs can be configured individually  
for all three output banks by the FSELx pins supporting systems with different but phase-aligned clock frequencies.  
The PLL of the MPC93H52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs  
and outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50transmission lines.  
Alternatively, each output can drive up to two series terminated transmission lines giving the device an effective fanout  
of 22.  
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis.  
The MPC93H52 is package in a 32-lead LQFP.  
© Motorola, Inc. 2004  
For More Information On This Product,  
Go to: www.freescale.com  

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