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MPC93H52ACR2 PDF预览

MPC93H52ACR2

更新时间: 2024-11-04 14:53:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
14页 385K
描述
PLL Based Clock Driver, 93H Series, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, LEAD FREE, LQFP-32

MPC93H52ACR2 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LEAD FREE, LQFP-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
Is Samacsys:N系列:93H
输入调节:STANDARDJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.024 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:11最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.3 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm最小 fmax:100 MHz
Base Number Matches:1

MPC93H52ACR2 数据手册

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3.3 V 1:11 LVCMOS Zero Delay  
Clock Generator  
MPC93H52  
NRND  
DATASHEET  
NRND – Not Recommend for New Designs  
The MPC93H52 is a 3.3 V compatible, 1:11 PLL based clock generator  
targeted for high performance clock tree applications. With output frequencies up  
to 240 MHz and output skews lower than 200 ps the device meets the needs of  
most demanding clock applications.  
MPC93H52  
Features  
Configurable 11 Outputs LVCMOS PLL Clock Generator  
Fully Integrated PLL  
LOW VOLTAGE  
3.3 V LVCMOS 1:11  
CLOCK GENERATOR  
Wide Range of Output Clock Frequency of 16.67 MHz to 240 MHz  
Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 32, 23,  
13 and 12  
3.3 V LVCMOS Compatible  
Maximum Output Skew of 200 ps  
Supports Zero-Delay Applications  
Designed for High-Performance Telecom, Networking and Computing  
Applications  
FA SUFFIX  
32-LEAD LQFP PACKAGE  
CASE 873A-03  
32-Lead LQFP Package  
32-Lead Pb-free Package Available  
Ambient Temperature Range — 0°C to +70°C  
Pin and Function Compatible to the MPC952  
Not Recommend for New Designs  
AC SUFFIX  
32-LEAD LQFP PACKAGE  
Pb-FREE PACKAGE  
CASE 873A-03  
Functional Description  
The MPC93H52 is a fully 3.3 V compatible PLL clock generator and clock driv-  
er. The device has the capability to generate output clock signals of 16.67 to 240  
MHz from external clock sources. The internal PLL is optimized for its frequency  
range and does not require external lock filter components. One output of the MPC93H52 has to be connected to the PLL feed-  
back input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency  
multiplication factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO  
in its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the  
FSELx pins supporting systems with different but phase-aligned clock frequencies.  
The PLL of the MPC93H52 minimizes the propagation delay and, therefore, supports zero-delay applications. All inputs and  
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 transmission lines. Alternatively,  
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.  
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The  
MPC93H52 is package in a 32-lead LQFP.  
MPC93H52 REVISION 5 FEBRUARY 15, 2013  
1
©2013 Integrated Device Technology, Inc.  

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