Datasheet > MPC9352FAR2

MPC9352FAR2

更新时间： 2024-02-21 15:43:08

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	188K
描述
PLL Based Clock Driver, 9352 Series, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, LQFP-32

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技术参数
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MPC9352FAR2 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	LQFP, QFP32,.35SQ,32	针数：	32
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.38	其他特性：	CAN ALSO OPERATE WITH 3.3V SUPPLY
输入调节：	STANDARD	JESD-30 代码：	S-PQFP-G32
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	11
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.2 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	7 mm	最小 fmax：	100 MHz

MPC9352FAR2 数据手册

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9352/D

Rev 3, 06/2003

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The MPC9352 is a 3.3V or 2.5V compatible, 1:11 PLL based clock

generator targeted for high performance clock tree applications. With

output frequencies up to 200 MHz and output skews lower than 200 ps

the device meets the needs of most demanding clock applications.

LOW VOLTAGE

3.3V/2.5V LVCMOS 1:11

CLOCK GENERATOR

Features

• Configurable 11 outputs LVCMOS PLL clock generator

• Fully integrated PLL

• Wide range of output clock frequency of 16.67 MHz to 200 MHz

• Multiplication of the input reference clock frequency by 3, 2, 1, 3B2,

2B3, 1B3 and 1B2

• 2.5V and 3.3V LVCMOS compatible

• Maximum output skew of 200 ps

• Supports zero–delay applications

• Designed for high–performance telecom, networking and computing

applications

• 32 lead LQFP package

• Ambient Temperature Range –40°C to +85°C

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

Functional Description

The MPC9352 is a fully 3.3V or 2.5V compatible PLL clock generator

and clock driver. The device has the capability to generate output clock

signals of 16.67 to 200 MHz from external clock sources. The internal PLL

optimized for its frequency range and does not require external look filter

components. One output of the MPC9352 has to be connected to the PLL

feedback input FB_IN to close the external PLL feedback path. The

output divider of this output setting determines the PLL frequency

multiplication factor. This multiplication factor, F_RANGE and the

reference clock frequency must be selected to situate the VCO in its

specified lock range. The frequency of the clock outputs can be

configured individually for all three output banks by the FSELx pins

supporting systems with different but phase-aligned clock frequencies.

The PLL of the MPC9352 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and

outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50Ω transmission lines. Alternatively,

each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.

The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The

MPC9352 is package in a 32 ld LQFP.

 Motorola, Inc. 2003

12 3 4 5 6 7...16

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MPC9352FAR2 替代型号

型号	品牌	替代类型	描述	数据表
PI6C2952FBEX	PERICOM	功能相似	PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, GREEN,

与MPC9352FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC93H51AC	NXP	获取价格	93H SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC93H51ACR2	IDT	获取价格	PLL Based Clock Driver, 93H Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
MPC93H51ACR2	NXP	获取价格	93H SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC93H51FA	MOTOROLA	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
MPC93H51FA	NXP	获取价格	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC
MPC93H52AC	IDT	获取价格	PLL Based Clock Driver, 93H Series, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC93H52AC	NXP	获取价格	93H SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD
MPC93H52ACR2	IDT	获取价格	PLL Based Clock Driver, 93H Series, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC93H52ACR2	NXP	获取价格	93H SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD
MPC93H52FA	NXP	获取价格	93H SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LQFP-

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