Datasheet > MPC9331FA

MPC9331FA

更新时间： 2024-11-04 19:52:03

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件逻辑集成电路
页数	文件大小	规格书
12页	314K
描述
9331 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32

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MPC9331FA 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	7 X 7 MM, LQFP-32
针数：	32	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.26
其他特性：	CAN ALSO OPERATE WITH 3.3V SUPPLY	系列：	9331
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.024 A
湿度敏感等级：	2	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	6	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	220
电源：	2.5/3.3 V	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.15 ns	座面最大高度：	1.6 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	7 mm	最小 fmax：	100 MHz
Base Number Matches：	1

MPC9331FA 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9331/D

Rev 4, 02/2003

The MPC9331 is a 3.3V compatible, 1:6 PLL based clock generator

targeted for high performance low-skew clock distribution in mid-range to

high-performance telecom, networking, and computing applications. With

output frequencies up to 240 MHz and output skews less than 150 ps, the

device meets the needs of most the demanding clock applications. The

MPC9331 is specified for the temperature range of 0°C to +70°C.

LOW VOLTAGE

3.3V LVCMOS 1:6

CLOCK GENERATOR

Features

• 1:6 PLL based low-voltage clock generator

• 3.3V power supply

• Generates clock signals up to 240 MHz

• Maximum output skew of 150 ps

• Differential LVPECL reference clock input

• Alternative LVCMOS PLL reference clock input

• Internal and external PLL feedback

• Supports zero-delay operation in external feedback mode

• PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2,

x/3 or x/4

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

• Synchronous output clock stop in logic low eliminates output runt pulses

• Power_down feature reduces output clock frequency

• Drives up to 12 clock lines

• 32 lead LQFP packaging

• Ambient temperature range 0°C to +70°C

• Internal Power–Up Reset

• Pin and function compatible to the MPC931

Functional Description

The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback

input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback

path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback

configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the

MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration

(divide-by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a

division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC

pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.

The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The

PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference

clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency

specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the

OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to

missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling

the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop

synchronously in logic low state, without the potential generation of runt pulses.

The MPC9331 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the

devices an effective fanout of 1:12. The device is packaged in a 7x7 mm 32-lead LQFP package.

For More Information On This Product,

Motorola, Inc. 2003

Go to: www.freescale.com

12 3 4 5 6 7...12

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与MPC9331FA相关器件

型号	品牌	获取价格	描述	数据表
MPC9331FAR2	NXP	获取价格	IC,1:6 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC9331FAR2	IDT	获取价格	PLL Based Clock Driver, 9331 Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC9350	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC9350AC	NXP	获取价格	IC,1:9 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC9350ACR2	NXP	获取价格	IC,1:9 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC9350D	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC9350FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC9350FAR2	NXP	获取价格	9350 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9350FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, PLASTIC,
MPC9351	FREESCALE	获取价格	Low Voltage PLL Clock Driver

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