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MPC9351FAR2 PDF预览

MPC9351FAR2

更新时间: 2024-11-04 15:44:11
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MPC9351FAR2 数据手册

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Low Voltage PLL Clock Driver  
MPC9351  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016  
DATA SHEET  
The MPC9351 is a 2.5V and 3.3V compatible, PLL based clock generator  
targeted for high performance clock distribution systems. With output  
frequencies of up to 200 MHz and a maximum output skew of 150ps, the  
MPC9351 is an ideal solution for the most demanding clock tree designs. The  
device offers 9 low-skew clock outputs, each is configurable to support the  
clocking needs of the various high-performance microprocessors including the  
PowerQUICC II integrated communication microprocessor. The extended  
temperature range of the MPC9351 supports telecommunication and networking  
requirements.The device employs a fully differential PLL design to minimize  
MPC9351  
LOW VOLTAGE  
2.5 V AND 3.3 V PLL  
CLOCK GENERATOR  
cycle-to-cycle and long-term jitter.  
Features  
9 Outputs LVCMOS PLL Clock Generator  
25 – 200MHz Output Frequency Range  
Fully Integrated PLL  
2.5V and 3.3V Compatible  
Compatible to Various Microprocessors Such as PowerQuicc II  
Supports Networking, Telecommunications and Computer Applications  
Configurable Outputs: Divide-by-2, 4 and 8 of VCO Frequency  
LVPECL and LVCMOS Compatible Inputs  
External Feedback Enables Zero-Delay Configurations  
Output Enable/disable and Static Test Mode (PLL Enable/Disable)  
Low Skew Characteristics: Maximum 150ps Output-to-Output  
Cycle-to-Cycle Jitter Max. 22ps RMS  
AC SUFFIX  
32-LEAD LQFP PACKAGE  
Pb-FREE PACKAGE  
CASE 873A-03  
32-Lead LQFP Package, Pb-Free  
Ambient Temperature Range -40°C to +85°C  
For functional replacement use 8T49N285  
Functional Description  
The MPC9351 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation  
of the MPC9351 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The  
reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to  
match the VCO frequency range. With available output dividers of divide-by-2, divide-by-4 and divide-by-8, the internal VCO of  
the MPC9351 is running at either 2x, 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs  
is either the one-half, one-fourth or one-eighth of the selected VCO frequency and can be configured for each output bank using  
the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output-to-input frequency ratios are 4:1, 2:1, 1:1, 1:2  
and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input  
(TCLK). The MPC9351 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test  
mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended  
for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification  
does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes  
the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase  
locked loop, also enabling the PLL to recover to normal operation. The MPC9351 is fully 2.5 V and 3.3 V compatible and requires  
no external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals, while the outputs provide  
LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission  
lines, each of the MPC9351 outputs can drive one or two traces giving the device an effective fanout of 1:18. The device is pack-  
aged in a 7x7 mm2 32-lead LQFP package.  
Application Information  
The fully integrated PLL of the MPC9351 allows the low-skew outputs to lock onto a clock input and distribute it with essentially  
zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between  
the outputs and the reference signal.  
MPC9351 REVISION 7 3/14/16  
1
©2016 Integrated Device Technology, Inc.  

MPC9351FAR2 替代型号

型号 品牌 替代类型 描述 数据表
MPC9351FA IDT

完全替代

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