Datasheet > MPC9350FAR2

MPC9350FAR2

更新时间： 2024-11-04 14:53:55

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件逻辑集成电路
页数	文件大小	规格书
9页	316K
描述
9350 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32

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MPC9350FAR2 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	LQFP, QFP32,.35SQ,32
针数：	32	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.47
其他特性：	ALSO OPERATE AT 3.3V SUPPLY	系列：	9350
输入调节：	MUX	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	最大I（ol）：	0.015 A
湿度敏感等级：	2	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	9	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	220
电源：	2.5/3.3 V	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.15 ns	座面最大高度：	1.6 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	7 mm	最小 fmax：	100 MHz
Base Number Matches：	1

MPC9350FAR2 数据手册

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9350/D

Rev 3, 01/2002

Freescale Semiconductor, Inc.

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The MPC9350 is a 2.5V and 3.3V compatible, PLL based clock gener-

ator targeted for high performance clock distribution systems. With output

frequencies of up to 200 MHz and maximum output skews of 150 ps the

MPC9350 is ideal for the most demanding clock tree designs. The device

offers 9 low skew clock outputs, each is configurable to support the clock-

ing needs of the various high-performance microprocessors including the

PowerQuicc II integrated communication microprocessor. The extended

temperature range of the MPC9350 supports telecommunication and net-

working requirements. The devices employs a fully differential PLL de-

sign to minimize cycle-to-cycle and long-term jitter.

LOW VOLTAGE

3.3V AND 2.5V PLL

CLOCK GENERATOR

Features

• 9 outputs LVCMOS PLL clock generator

• 25 – 200 MHz output frequency range

• 2.5V and 3.3V compatible

• Compatible to various microprocessor such as PowerQuicc II

• Supports networking, telecommunications and computer applications

• Fully integrated PLL

• Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

• Selectable output to input frequency ratio of 8:1, 4:1, 2:1 or 1:1

• Oscillator or crystal reference inputs

• Internal PLL feedback

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

• Output disable

• PLL enable/disable

• Low skew characteristics: maximum 150 ps output-to-output

• 32 lead LQFP package

• Temperature range –40°C to +85°C

Functional Description

The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference

clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference

clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable

PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects

between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match

the VCO frequency range. With the available feedback output dividers the internal VCO of the MPC9350 is running at either 16x

or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one

eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD

pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal

oscillator inputs or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode

when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly

to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purpose. This test

mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting

the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The MPC9350

is fully 2.5V and 3.3V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no

external components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept LVCMOS signals

while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 W transmission lines. For series

terminated transmission lines, each of the MPC9350 outputs can drive one or two traces giving the devices an effective fanout of

1:18. The device is packaged in a 7x7 mm²32-lead LQFP package.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

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与MPC9350FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9351	FREESCALE	获取价格	Low Voltage PLL Clock Driver
MPC9351AC	NXP	获取价格	9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9351ACR2	NXP	获取价格	9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9351D	FREESCALE	获取价格	Low Voltage PLL Clock Driver
MPC9351FA	IDT	获取价格	PLL Based Clock Driver, 9351 Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
MPC9351FA	MOTOROLA	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32
MPC9351FAR2	IDT	获取价格	暂无描述
MPC9351FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32
MPC9352	MOTOROLA	获取价格	3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
MPC9352AC	NXP	获取价格	9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD

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