Datasheet > MPC9351

MPC9351

更新时间： 2024-11-04 04:14:47

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		时钟驱动器
页数	文件大小	规格书
12页	309K
描述
Low Voltage PLL Clock Driver

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MPC9351 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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by MPC9351/D

The MPC9351 is a 2.5V and 3.3V compatible, PLL based clock

generator targeted for high performance clock distribution systems. With

output frequencies of up to 200 MHz and a maximum output skew of 150

ps the MPC9351 is an ideal solution for the most demanding clock tree

designs. The device offers 9 low skew clock outputs, each is configurable

to support the clocking needs of the various high-performance

microprocessors including the PowerQuicc II integrated communication

microprocessor. The extended temperature range of the MPC9351

supports telecommunication and networking requirements.The devices

employs a fully differential PLL design to minimize cycle-to-cycle and

long-term jitter.

LOW VOLTAGE

2.5V AND 3.3V PLL

CLOCK GENERATOR

Features

• 9 outputs LVCMOS PLL clock generator

• 25 - 200 MHz output frequency range

• Fully integrated PLL

• 2.5V and 3.3V compatible

• Compatible to various microprocessors such as PowerQuicc II

• Supports networking, telecommunications and computer applications

• Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

• LVPECL and LVCMOS compatible inputs

• External feedback enables zero-delay configurations

• Output enable/disable and static test mode (PLL enable/disable)

• Low skew characteristics: maximum 150 ps output-to-output

• Cycle-to-cycle jitter max. 22 ps RMS

FA SUFFIX

LQFP PACKAGE

CASE 873A–02

• 32 lead LQFP package

• Ambient Temperature Range –40°C to +85°C

Functional Description

The MPC9351 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation

of the MPC9351 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The

reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to

match the VCO frequency range. With available output dividers of divide-by-2, divide-by-4 and divide-by-8 the internal VCO of the

MPC9351 is running at either 2x, 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is

either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the

FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and

1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK).

The MPC9351 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the

selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system

diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply.

The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose

lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also

enabling the PLL to recover to normal operation. The MPC9351 is fully 2.5V and 3.3V compatible and requires no external loop

filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible

levels with the capability to drive terminated 50

MPC9351 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm

32-lead LQFP package.

transmission lines. For series terminated transmission lines, each of the

Application Information

The fully integrated PLL of the MPC9351 allows the low skew outputs to lock onto a clock input and distribute it with essentially

zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between

the outputs and the reference signal.

06/01

For More Information On This Product,

Go to: www.freescale.c^Ro^Em^{V 1}

Motorola, Inc. 2001

12 3 4 5 6 7...12

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与MPC9351相关器件

型号	品牌	获取价格	描述	数据表
MPC9351AC	NXP	获取价格	9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9351ACR2	NXP	获取价格	9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9351D	FREESCALE	获取价格	Low Voltage PLL Clock Driver
MPC9351FA	IDT	获取价格	PLL Based Clock Driver, 9351 Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
MPC9351FA	MOTOROLA	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32
MPC9351FAR2	IDT	获取价格	暂无描述
MPC9351FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32
MPC9352	MOTOROLA	获取价格	3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
MPC9352AC	NXP	获取价格	9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD
MPC9352FA	NXP	获取价格	9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LQFP

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