Datasheet > MPC9350ACR2

MPC9350ACR2

更新时间： 2024-11-04 19:43:15

品牌	Logo	应用领域
恩智浦 - NXP		输出元件
页数	文件大小	规格书
12页	302K
描述
IC,1:9 OUTPUT,CMOS,QFP,32PIN,PLASTIC

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MPC9350ACR2 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	QFP, QFP32,.35SQ,32	Reach Compliance Code：	unknown
风险等级：	5.8	JESD-30 代码：	S-PQFP-G32
最大I（ol）：	0.015 A	湿度敏感等级：	3
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP32,.35SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	2.5/3.3 V	认证状态：	Not Qualified
子类别：	Clock Drivers	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	Base Number Matches：	1

MPC9350ACR2 数据手册

MPC9350

Rev 6, 4/2005

Freescale Semiconductor

Technical Data

Low Voltage PLL Clock Driver

MPC9350

The MPC9350 is a 2.5 V and 3.3 V compatible, PLL-based clock generator

targeted for high performance clock distribution systems. With output

frequencies of up to 200 MHz and maximum output skews of 150 ps, the

MPC9350 is ideal for the most demanding clock tree designs. The device offers

9 low skew clock outputs, with each one configurable to support the clocking

needs of the various high-performance microprocessors, including the

PowerQUICC II integrated communication microprocessor. The extended

temperature range of the MPC9350 supports telecommunication and networking

requirements. The device employs a fully differential PLL design to minimize

cycle-to-cycle and long-term jitter.

LOW VOLTAGE

3.3 V AND 2.5 V PLL

CLOCK GENERATOR

Features

•

9 output LVCMOS PLL clock generator

25 – 200 MHz output frequency range

2.5 V and 3.3 V compatible

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

Compatible to various microprocessors such as PowerQuicc II

Supports networking, telecommunications and computer applications

Fully integrated PLL

Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

Selectable output to input frequency ratio of 8:1, 4:1, 2:1 or 1:1

Oscillator or crystal reference inputs

Internal PLL feedback

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

Output disable

PLL enable/disable

Low skew characteristics: maximum 150 ps output-to-output

32-lead LQFP package

32-lead Pb-free Package Available

Temperature range –40°C to +85°C

Functional Description

The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference

clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference

clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable

PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects

between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match

the VCO frequency range. With the available feedback output dividers, the internal VCO of the MPC9350 is running at either 16x

or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one

eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD

pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal

oscillator input or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode

when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly

to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purposes. This

test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by

deasserting the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path.

The MPC9350 is fully 2.5 V and 3.3 V compatible and requires no external loop filter components. The on-chip crystal oscillator

requires no external components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission

lines. For series terminated transmission lines, each of the MPC9350 outputs can drive one or two traces giving the device an

effective fanout of 1:18. The device is packaged in a 7x7 mm²32-lead LQFP package.

12 3 4 5 6 7...12

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与MPC9350ACR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9350D	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC9350FA	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC9350FAR2	NXP	获取价格	9350 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9350FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, PLASTIC,
MPC9351	FREESCALE	获取价格	Low Voltage PLL Clock Driver
MPC9351AC	NXP	获取价格	9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9351ACR2	NXP	获取价格	9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9351D	FREESCALE	获取价格	Low Voltage PLL Clock Driver
MPC9351FA	IDT	获取价格	PLL Based Clock Driver, 9351 Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
MPC9351FA	MOTOROLA	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32

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