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FDM84100 PDF预览

FDM84100

更新时间: 2024-02-03 03:30:47
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
7页 234K
描述
Power Field-Effect Transistor

FDM84100 技术参数

生命周期:Transferred包装说明:,
Reach Compliance Code:compliant风险等级:5.76
Base Number Matches:1

FDM84100 数据手册

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Electrical Characteristics TJ = 25 °C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BVDSS  
Drain to Source Breakdown Voltage  
ID = 250 μA, VGS = 0 V  
100  
V
ΔBVDSS  
ΔTJ  
Breakdown Voltage Temperature  
Coefficient  
I
D = 250 μA, referenced to 25 °C  
74  
mV/°C  
IDSS  
IGSS  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
VDS = 80 V, VGS = 0 V  
VGS = ±20 V, VDS = 0 V  
1
μA  
±100  
nA  
On Characteristics  
VGS(th)  
Gate to Source Threshold Voltage  
VGS = VDS, ID = 250 μA  
2
3.1  
-9  
4
V
ΔVGS(th)  
ΔTJ  
Gate to Source Threshold Voltage  
Temperature Coefficient  
I
D = 250 μA, referenced to 25 °C  
VGS = 10 V, ID = 7 A  
GS = 6 V, ID = 5.5 A  
mV/°C  
16  
24  
30  
17  
20  
32  
38  
rDS(on)  
gFS  
Static Drain to Source On Resistance  
Forward Transconductance  
V
mΩ  
VGS = 10 V, ID = 7 A, TJ = 125 °C  
VDD = 5 V, ID = 7 A  
S
Dynamic Characteristics  
Ciss  
Coss  
Crss  
Rg  
Input Capacitance  
734  
168  
6.6  
980  
225  
15  
pF  
pF  
pF  
Ω
VDS = 50 V, VGS = 0 V  
f = 1 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
0.1  
1.3  
3
Switching Characteristics  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Rise Time  
8.4  
2.6  
14  
17  
10  
25  
10  
16  
11  
ns  
ns  
VDD = 50 V, ID = 7 A  
VGS = 10 V, RGEN = 6 Ω  
Turn-Off Delay Time  
Fall Time  
ns  
2.8  
11  
ns  
Total Gate Charge  
Total Gate Charge  
Gate to Source Charge  
Gate to Drain “Miller” Charge  
VGS = 0 V to 10 V  
VGS = 0 V to 6 V  
nC  
nC  
nC  
nC  
Qg(TOT)  
7.3  
3.4  
2.5  
VDD = 50 V  
D = 7 A  
I
Qgs  
Qgd  
Drain-Source Diode Characteristics  
VSD  
trr  
Source to Drain Diode Forward Voltage  
Reverse Recovery Time  
VGS = 0 V, IS = 7 A  
(Note 2)  
0.8  
43  
44  
1.2  
70  
71  
V
ns  
nC  
IF = 7 A, di/dt = 100 A/μs  
Qrr  
Reverse Recovery Charge  
NOTES:  
2
1. R  
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R  
is guaranteed by design while R  
is determined by  
θCA  
θJA  
θJC  
the user's board design.  
b.160 °C/W when mounted on  
a minimum pad of 2 oz copper  
a. 60 °C/W when mounted on  
a 1 in padof 2oz copper  
2
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.  
o
3. E of 121 mJ is based on starting T = 25 C, L = 3 mH, I = 9 A, V = 100 V, V = 10 V. 100% tested at L = 0.1 mH, I = 30 A.  
AS  
J
AS  
DD  
GS  
AS  
4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area.  
2
www.fairchildsemi.com  
©2014 Fairchild Semiconductor Corporation  
FDMD84100 Rev.C  

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