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CY7C1351G-133BGI PDF预览

CY7C1351G-133BGI

更新时间： 2024-09-16 03:02:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
14页 395K
描述
4-Mbit (128K x 36) Flow-through SRAM with NoBL⑩ Architecture

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CY7C1351G-133BGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：22 X 14 MM, 2.40 MM HEIGHT, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.85最长访问时间：6.5 ns
其他特性：FLOW THROUGH ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：119字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.225 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1351G-133BGI 数据手册

 浏览型号CY7C1351G-133BGI的Datasheet PDF文件第2页浏览型号CY7C1351G-133BGI的Datasheet PDF文件第3页浏览型号CY7C1351G-133BGI的Datasheet PDF文件第4页浏览型号CY7C1351G-133BGI的Datasheet PDF文件第5页浏览型号CY7C1351G-133BGI的Datasheet PDF文件第6页浏览型号CY7C1351G-133BGI的Datasheet PDF文件第7页 
CY7C1351G  
4-Mbit (128K x 36) Flow-through SRAM  
with NoBL™ Architecture  
Functional Description[1]  
Features  
• Can support up to 133-MHz bus operations with zero  
wait states  
The CY7C1351G is a 3.3V, 128K x 36 Synchronous  
Flow-through Burst SRAM designed specifically to support  
unlimited true back-to-back Read/Write operations without the  
insertion of wait states. The CY7C1351G is equipped with the  
advanced No Bus Latency™ (NoBL™) logic required to  
enable consecutive Read/Write operations with data being  
transferred on every clock cycle. This feature dramatically  
improves the throughput of data through the SRAM, especially  
in systems that require frequent Write-Read transitions.  
— Data is transferred on every clock  
• Pin compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Registered inputs for flow-through operation  
• Byte Write capability  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
• 128K x 36 common I/O architecture  
• 2.5V/3.3V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
Write operations are controlled by the four Byte Write Select  
(BW[A:D]) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• Asynchronous Output Enable  
• Available in lead-free 100-Pin TQFP package, lead-free  
and non-lead-free 119-Ball BGA package  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Logic Block Diagram  
ADDRESS  
A0, A1, A  
REGISTER  
A1  
A1'  
A0'  
D1  
A0  
Q1  
Q0  
D0  
MODE  
BURST  
LOGIC  
CE  
ADV/LD  
C
CLK  
CEN  
C
WRITE ADDRESS  
REGISTER  
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD  
A
B
U
F
MEMORY  
ARRAY  
BWA  
BWB  
BWC  
BWD  
WRITE  
DRIVERS  
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
A
B
C
D
A
M
P
F
E
R
S
S
WE  
E
N
G
INPUT  
REGISTER  
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
Control  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05513 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 4, 2006  
[+] Feedback  
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