Datasheet > CY7C135-25JCT

CY7C135-25JCT

更新时间： 2024-11-27 06:44:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
12页	401K
描述
Dual-Port SRAM, 4KX8, 25ns, CMOS, PQCC52, PLASTIC, LCC-52

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CY7C135-25JCT 数据手册

CY7C135, CY7C135A

CY7C1342

4K x 8 Dual-Port Static RAM and 4K x 8

Dual-Port SRAM with Semaphores

Features

Functional Description

■

True dual-ported memory cells, which allow simultaneous

reads of the same memory location

The CY7C135/135A^[1]and CY7C1342 are high speed CMOS 4K

x 8 dual-port static RAMs. The CY7C1342 includes semaphores

that provide a means to allocate portions of the dual-port RAM

or any shared resource. Two ports are provided permitting

independent, asynchronous access for reads and writes to any

location in memory. Application areas include interpro-

■

4K x 8 organization

0.65 micron CMOS for optimum speed and power

High speed access: 15 ns

cessor/multiprocessor

designs,

communications

status

buffering, and dual-port video/graphics memory.

Low operating power: I_CC= 160 mA (max)

Fully asynchronous operation

Automatic power down

Each port has independent control pins: chip enable (CE), read

or write enable (R/W), and output enable (OE). The

CY7C135/135A is suited for those systems that do not require

on-chip arbitration or are intolerant of wait states. Therefore, the

user must be aware that simultaneous access to a location is

possible. Semaphores are offered on the CY7C1342 to assist in

arbitrating between ports. The semaphore logic is comprised of

eight shared latches. Only one side can control the latch

(semaphore) at any time. Control of a semaphore indicates that

a shared resource is in use. An automatic power down feature is

controlled independently on each port by a chip enable (CE) pin

or SEM pin (CY7C1342 only).

Semaphores included on the 7C1342 to permit software

handshaking between ports

■

Available in 52-pin PLCC

Pb-free packages available

The CY7C135/135A and CY7C1342 are available in 52-pin

PLCC.

Logic Block Diagram

R/W_L

R/W_R

CE_L

OE_L

CE_R

OE_R

I/O_7L

I/O_7R

I/O_0R

I/O

CONTROL

I/O

CONTROL

I/O_0L

A_11L

A_11R

ADDRESS

DECODER

ADDRESS

DECODER

MEMORY

ARRAY

A_0L

A_0R

SEMAPHORE

ARBITRATION

(7C1342 only)

CE_L

OE_L

CE_R

OE_R

R/W_L

R/W_R

(7C1342 only)

SEM_R

SEM_L

Note

1. CY7C135 and CY7C135A are functionally identical

Cypress Semiconductor Corporation

Document #: 38-06038 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised December 09, 2008

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与CY7C135-25JCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C135-25JI	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-25JXC	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C1352-80AC	CYPRESS	获取价格	256K x18 Pipelined SRAM with NoBL Architecture
CY7C1352B	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-100AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-100ACT	CYPRESS	获取价格	暂无描述
CY7C1352B-133AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-143AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-143ACT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1352B-150AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture

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