Datasheet > 存储 > SRAM> CY7C135-25JI

CY7C135-25JI

更新时间： 2024-11-25 22:02:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
12页	554K
描述
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

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中文翻译

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CY7C135-25JI 数据手册

CY7C135

CY7C1342

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port

SRAM with Semaphores

Features

Functional Description

• True Dual-Ported memory cells which allow simulta-

The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8

dual-port static RAMs. The CY7C1342 includes semaphores

that provide a means to allocate portions of the dual-port RAM

or any shared resource. Two ports are provided permitting in-

dependent, asynchronous access for reads and writes to any

location in memory. Application areas include interproces-

sor/multiprocessor designs, communications status buffering,

and dual-port video/graphics memory.

neous reads of the same memory location

• 4K x 8 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

• Low operating power: I_CC= 160 mA (max.)

• Fully asynchronous operation

• Automatic power-down

• Semaphoresincludedonthe7C1342topermitsoftware

handshaking between ports

• Available in 52-pin PLCC

Each port has independent control pins: chip enable (CE),

read or write enable (R/W), and output enable (OE). The

CY7C135 is suited for those systems that do not require

on-chip arbitration or are intolerant of wait states. Therefore,

the user must be aware that simultaneous access to a location

is possible. Semaphores are offered on the CY7C1342 to as-

sist in arbitrating between ports. The semaphore logic is com-

prised of eight shared latches. Only one side can control the

latch (semaphore) at any time. Control of a semaphore indi-

cates that a shared resource is in use. An automatic pow-

er-down feature is controlled independently on each port by a

chip enable (CE) pin or SEM pin (CY7C1342 only).

The CY7C135 and CY7C1342 are available in 52-pin PLCC.

Logic Block Diagram

R/W

I/O

CONTROL

I/O

CONTROL

I/O

11L

11R

ADDRESS

DECODER

ADDRESS

DECODER

MEMORY

ARRAY

SEMAPHORE

ARBITRATION

(7C1342 only)

R/W

(7C1342 only)

1342–1

SEM

Cypress Semiconductor Corporation

Document #: 38-06038 Rev. *B

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised June 22, 2004

12 3 4 5 6 7...12

中文翻译

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与CY7C135-25JI相关器件

型号	品牌	获取价格	描述	数据表
CY7C135-25JXC	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C1352-80AC	CYPRESS	获取价格	256K x18 Pipelined SRAM with NoBL Architecture
CY7C1352B	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-100AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-100ACT	CYPRESS	获取价格	暂无描述
CY7C1352B-133AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-143AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-143ACT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1352B-150AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-166AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture

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