Datasheet > CY7C1352G_12

CY7C1352G_12

更新时间： 2024-11-26 12:22:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
20页	538K
描述
4-Mbit (256 K Ã 18) Pipelined SRAM with NoBLâ¢ Architecture

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CY7C1352G_12 数据手册

CY7C1352G

4-Mbit (256 K × 18) Pipelined SRAM with

NoBL™ Architecture

4-Mbit (256

K × 18) Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

■ Pin compatible and functionally equivalent to ZBT™ devices

The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined

burst SRAM designed specifically to support unlimited true

back-to-back read/write operations without the insertion of wait

states. The CY7C1352G is equipped with the advanced No Bus

Latency™ (NoBL™) logic required to enable consecutive

read/write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of the

SRAM, especially in systems that require frequent write/read

transitions.

■ Internally self-timed output buffer control to eliminate the need

to use OE

■ Byte write capability

■ 256 K × 18 common I/O architecture

■ 3.3 V core power supply (V_DD

)

■ 2.5 V/3.3 V I/O power supply (V_DDQ

)

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which, when

deasserted, suspends operation and extends the previous clock

cycle. Maximum access delay from the clock rise is 4.0 ns

(133-MHz device).

■ Fast clock-to-output times

❐ 4.0 ns (for 133-MHz device)

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

■ Asynchronous output enable (OE)

Write operations are controlled by the two byte write select

(BW_[A:B]) and a write enable (WE) input. All writes are conducted

with on-chip synchronous self-timed write circuitry.

■ Available in Pb-free 100-pin TQFP package

■ Burst capability – linear or interleaved burst order

■ ZZ sleep mode option and stop clock option

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated during

the data portion of a write sequence.

Selection Guide

Description

133 MHz Unit

Maximum access time

4.0

225

Maximum operating current

Maximum CMOS standby current

Cypress Semiconductor Corporation

Document Number: 38-05514 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 21, 2012

12 3 4 5 6 7...20

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与CY7C1352G_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1352G_13	CYPRESS	获取价格	4-Mbit (256 K x 18) Pipelined SRAM with NoBLâ
CY7C1352G-133AXC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-133AXC	INFINEON	获取价格	Synchronous SRAM
CY7C1352G-133AXI	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-166AXC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-166AXI	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-166AXIT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1352G-200AXC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-200AXI	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-250AXC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

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