Datasheet > CY7C1353-50ACT

CY7C1353-50ACT

更新时间： 2024-11-26 20:49:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
13页	277K
描述
ZBT SRAM, 256KX18, 12ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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技术参数
数据手册

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CY7C1353-50ACT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.76
最长访问时间：	12 ns	其他特性：	SELF TIMED WRITE
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

CY7C1353-50ACT 数据手册

353

CY7C1353

256Kx18 Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

• Pin compatible and functionally equivalent to ZBT™

The CY7C1353 is a 3.3V, 256K by 18 Synchronous

Flow-Through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1353 is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to en-

able consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data through the SRAM, especially in sys-

tems that require frequent Write-Read transitions. The

CY7C1353 is pin/functionally compatible to ZBT™ SRAMs

MCM63Z819 and MT55L256L18F.

devices MCM63Z819 and MT55L256L18F

• Supports 66-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for Flow-Through operation

• Byte Write capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted sus-

pends operation and extends the previous clock cycle. Maxi-

mum access delay from the clock rise is 11.0 ns (66-MHz de-

vice).

• Fast clock-to-output times

— 11.0 ns (for 66-MHz device)

— 12.0 ns (for 50-MHz device)

— 14.0 ns (for 40-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

• Low standby power

Write operations are controlled by the four Byte Write Select

(BWS_[1:0]) and a Write Enable (WE) input. All writes are con-

ducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

[17:0]

CEN

CONTROL

256KX18

and WRITE

LOGIC

MEMORY

[15:0]

[1:0]

ARRAY

BWS

[1:0]

Mode

Selection Guide

7C1353-66

11.0

7C1353-50

12.0

7C1353-40

14.0

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Commercial

250 mA

5 mA

200 mA

5 mA

175 mA

5 mA

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05081 Rev. **

Revised September 4, 2001

12 3 4 5 6 7...13

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与CY7C1353-50ACT相关器件

型号	品牌	获取价格	描述	数据表
CY7C135-35JC	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-35JCR	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-35JCT	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-35JI	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-35JIR	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-35JIT	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C1353-66AC	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353-66ACT	CYPRESS	获取价格	暂无描述
CY7C1353B	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-100AC	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture

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