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CY7C1353F-100AI PDF预览

CY7C1353F-100AI

更新时间： 2024-11-25 21:53:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
13页 324K
描述
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

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中文翻译

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CY7C1353F-100AI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.82最长访问时间：8 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.205 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

CY7C1353F-100AI 数据手册

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CY7C1353F  
4-Mb (256K x 18) Flow-through SRAM with NoBL™ Architecture  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Functional Description[1]  
Features  
• Can support up to 133-MHz bus operations with zero  
wait states  
— Data is transferred on every clock  
The CY7C1353F is a 3.3V, 256K x 18 Synchronous  
• Pin compatible and functionally equivalent to ZBT™  
Flow-through Burst SRAM designed specifically to support  
devices  
unlimited true back-to-back Read/Write operations without the  
• Internally self-timed output buffer control to eliminate  
insertion of wait states. The CY7C1353F is equipped with the  
advanced No Bus Latency™ (NoBL™) logic required to  
enable consecutive Read/Write operations with data being  
transferred on every clock cycle. This feature dramatically  
improves the throughput of data through the SRAM, especially  
in systems that require frequent Write-Read transitions.  
the need to use OE  
• Registered inputs for flow-through operation  
• Byte Write capability  
• 256K x 18 common I/O architecture  
• 2.5V / 3.3V I/O power supply  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
— 7.5 ns (for 117-MHz device)  
— 8.0 ns (for 100-MHz device)  
— 11.0 ns (for 66-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
• JEDEC-standard 100 TQFP package  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
Write operations are controlled by the two Byte Write Select  
(BW[A:B]) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
Logic Block Diagram  
ADDRESS  
REGISTER  
A0, A1, A  
A1  
A1'  
A0'  
D1  
A0  
Q1  
Q0  
D0  
MODE  
BURST  
LOGIC  
CE  
ADV/LD  
C
CLK  
CEN  
C
WRITE ADDRESS  
REGISTER  
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD  
A
B
U
F
MEMORY  
ARRAY  
BW  
A
WRITE  
DRIVERS  
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
S
T
E
E
R
I
DQs  
DQP  
DQP  
BW  
B
A
B
A
M
P
F
E
R
S
S
WE  
E
N
G
INPUT  
REGISTER  
E
OE  
READ LOGIC  
CE  
CE  
CE  
1
2
3
SLEEP  
CONTROL  
ZZ  
1
Note:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05212 Rev. *B  
Revised January 13, 2004  
1234567...13

中文翻译

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