Datasheet > CY7C1354A_04

CY7C1354A_04

更新时间： 2024-11-26 05:19:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	403K
描述
256K x 36/512K x 18 Pipelined SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1354A_04 数据手册

CY7C1354A

CY7C1356A

256K x 36/512K x 18 Pipelined SRAM

with NoBL™ Architecture

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

Features

• Zero Bus Latency™, no dead cycles between Write and

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE, CE₂, and CE₃), Cycle Start Input (ADV/LD),

Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,

and BWd), and Read-Write Control (WEN). BWc and BWd

apply to CY7C1354A only.

Address and control signals are applied to the SRAM during

one clock cycle, and two cycles later, its associated data

occurs, either Read or Write.

Read cycles

• Fast clock speed: 200, 166, 133, 100 MHz

• Fast access time: 3.2, 3.6, 4.2, 5.0 ns

• Internally synchronized registered outputs eliminate

the need to control OE

• Single 3.3V –5% and +5% power supply V_CC

• Separate V_CCQfor 3.3V or 2.5V I/O

clock enable (CEN) pin allows operation of the

CY7C1354A/CY7C1356A to be suspended as long as

necessary. All synchronous inputs are ignored when (CEN) is

HIGH and the internal device registers will hold their previous

values.

• Single WEN (Read/Write) control pin

• Positive clock-edge triggered, address, data, and

control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

There are three chip enable pins (CE, CE₂, CE₃) that allow the

user to deselect the device when desired. If any one of these

three are not active when ADV/LD is LOW, no new memory

operation can be initiated and any burst cycle in progress is

stopped. However, any pending data transfers (Read or Write)

will be completed. The data bus will be in high-impedance

state two cycles after chip is deselected or a Write cycle is

initiated.

The CY7C1354A and CY7C1356A have an on-chip two-bit

burst counter. In the burst mode, the CY7C1354A and

CY7C1356A provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is

defined by the MODE input pin. The MODE pin selects

between linear and interleaved burst sequence. The ADV/LD

signal is used to load a new external address (ADV/LD = LOW)

or increment the internal burst counter (ADV/LD = HIGH)

Output Enable (OE), Sleep Enable (ZZ) and burst sequence

select (MODE) are the asynchronous signals. OE can be used

to disable the outputs at any given time. ZZ may be tied to

LOW if it is not used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

• Individual byte Write (BWa–BWd) control (may be tied

LOW)

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Automatic power-down feature available using ZZ

mode or CE select

• JTAG boundary scan

• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid

Array), and 100-pin TQFP packages

Functional Description

The CY7C1354A and CY7C1356A SRAMs are designed to

eliminate dead cycles when transitioning from Read to Write

or vice versa. These SRAMs are optimized for 100% bus utili-

zation and achieve Zero Bus Latency (ZBL)/No Bus

Latency (NoBL). They integrate 262,144 × 36 and 524,288

× 18 SRAM cells, respectively, with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. These employ high-speed, low-power CMOS

designs using advanced triple-layer polysilicon, double-layer

metal technology. Each memory cell consists of four

transistors and two high-valued resistors.

Selection Guide

7C1354A-166

7C1356A-166

7C1354A-133

7C1356A-133

7C1354A-200

3.2

7C1356A-100 Unit

Maximum Access Time

3.6

480

4.2

410

5.0

350

Maximum Operating Current

Commercial

560

Maximum CMOS Standby Current Commercial

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05161Rev. *E

Revised April 5, 2004

12 3 4 5 6 7...28

中文翻译

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与CY7C1354A_04相关器件

型号	品牌	获取价格	描述	数据表
CY7C1354A-100AC	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1354A-100ACI	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354A-100BGCI	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354A-133AC	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1354A-133ACI	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354A-133BGC	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL⑩
CY7C1354A-133BGC	ROCHESTER	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1354A-133BGCI	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354A-133BGCT	CYPRESS	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1354A-133BGI	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL⑩

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