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CY7C1353G-100AXC PDF预览

CY7C1353G-100AXC

更新时间： 2024-11-26 03:03:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
13页 219K
描述
4-Mbit (256K x 18) Flow-through SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1353G-100AXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：1 week
风险等级：2.09最长访问时间：8 ns
其他特性：FLOW-THROUGH ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

CY7C1353G-100AXC 数据手册

 浏览型号CY7C1353G-100AXC的Datasheet PDF文件第2页浏览型号CY7C1353G-100AXC的Datasheet PDF文件第3页浏览型号CY7C1353G-100AXC的Datasheet PDF文件第4页浏览型号CY7C1353G-100AXC的Datasheet PDF文件第5页浏览型号CY7C1353G-100AXC的Datasheet PDF文件第6页浏览型号CY7C1353G-100AXC的Datasheet PDF文件第7页 
CY7C1353G  
PRELIMINARY  
4-Mbit (256K x 18) Flow-through SRAM  
with NoBL™ Architecture  
Functional Description[1]  
Features  
• Can support up to 133-MHz bus operations with zero  
wait states  
The CY7C1353G is a 3.3V, 256K x 18 Synchronous  
Flow-through Burst SRAM designed specifically to support  
unlimited true back-to-back Read/Write operations without the  
insertion of wait states. The CY7C1353G is equipped with the  
advanced No Bus Latency™ (NoBL™) logic required to  
enable consecutive Read/Write operations with data being  
transferred on every clock cycle. This feature dramatically  
improves the throughput of data through the SRAM, especially  
in systems that require frequent Write-Read transitions.  
— Data is transferred on every clock  
• Pin compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Registered inputs for flow-through operation  
• Byte Write capability  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
• 256K x 18 common I/O architecture  
• 2.5V / 3.3V I/O power supply  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
Write operations are controlled by the two Byte Write Select  
(BW[A:B]) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
— 7.5 ns (for 117-MHz device)  
— 8.0 ns (for 100-MHz device)  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
• Pb-Free 100 TQFP package  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Logic Block Diagram  
ADDRESS  
REGISTER  
A0, A1, A  
A1  
A1'  
A0'  
D1  
A0  
Q1  
Q0  
D0  
MODE  
BURST  
LOGIC  
CE  
ADV/LD  
C
CLK  
CEN  
C
WRITE ADDRESS  
REGISTER  
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD  
A
B
U
F
MEMORY  
ARRAY  
BW  
A
WRITE  
DRIVERS  
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
S
T
E
E
R
I
DQs  
DQP  
DQP  
BW  
B
A
B
A
M
P
F
E
R
S
S
WE  
E
N
G
INPUT  
REGISTER  
E
OE  
READ LOGIC  
CE  
CE  
CE  
1
2
3
SLEEP  
CONTROL  
ZZ  
Note:  
1.For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05515 Rev. *A  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised October 22, 2004  
1234567...13

中文翻译

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CY7C1353G-100AXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1353G-100AXCT CYPRESS

完全替代

 ZBT SRAM, 256KX18, 8ns, CMOS, PQFP100,
CY7C1353G-133AXC CYPRESS

功能相似

 4-Mbit (256K x 18) Flow-through SRAM with NoB

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CY7C1353G-100AXI CYPRESS

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CY7C1353G-133AXC CYPRESS

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 		4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-133AXCT CYPRESS

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 		ZBT SRAM, 256KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, T
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 		4-Mbit (256K x 18) Flow-through SRAM with NoB
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 		256K x 36/512K x 18 Pipelined SRAM with NoBL⑩
CY7C1354A-100AC ROCHESTER

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