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CY7C1353G-100AXCT PDF预览

CY7C1353G-100AXCT

更新时间： 2024-11-26 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
19页 552K
描述
ZBT SRAM, 256KX18, 8ns, CMOS, PQFP100,

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中文翻译

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CY7C1353G-100AXCT 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：ActiveReach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.77Is Samacsys：N
最长访问时间：8 ns最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e4内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL电源：2.5/3.3,3.3 V
认证状态：Not Qualified最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.205 mA表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
Base Number Matches：1

CY7C1353G-100AXCT 数据手册

 浏览型号CY7C1353G-100AXCT的Datasheet PDF文件第2页浏览型号CY7C1353G-100AXCT的Datasheet PDF文件第3页浏览型号CY7C1353G-100AXCT的Datasheet PDF文件第4页浏览型号CY7C1353G-100AXCT的Datasheet PDF文件第5页浏览型号CY7C1353G-100AXCT的Datasheet PDF文件第6页浏览型号CY7C1353G-100AXCT的Datasheet PDF文件第7页 
CY7C1353G  
4-Mbit (256 K × 18) Flow-Through SRAM  
with NoBL™ Architecture  
4-Mbit (256  
K × 18) Flow-Through SRAM with NoBL™ Architecture  
Features  
Functional Description  
■ Supports up to 100-MHz bus operations with zero wait states  
❐ Data is transferred on every clock  
The CY7C1353G is a 3.3 V, 256 K × 18 synchronous  
flow-through burst SRAM designed specifically to support  
unlimited true back-to-back read/write operations without the  
insertion of wait states. The CY7C1353G is equipped with the  
advanced No Bus Latency™ (NoBL™) logic required to enable  
consecutive read/write operations with data being transferred on  
every clock cycle. This feature dramatically improves the  
throughput of data through the SRAM, especially in systems that  
require frequent write-read transitions.  
■ Pin compatible and functionally equivalent to ZBT™ devices  
■ Internally self timed output buffer control to eliminate the need  
to use OE  
■ Registered inputs for flow-through operation  
■ Byte write capability  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. The clock input is qualified by the  
clock enable (CEN) signal, which when deasserted suspends  
operation and extends the previous clock cycle. Maximum  
access delay from the clock rise is 8.0 ns (100-MHz device).  
■ 256 K × 18 common I/O architecture  
■ 2.5 V / 3.3 V I/O power supply (VDDQ  
)
■ Fast clock-to-output times  
❐ 8.0 ns (for 100-MHz device)  
Write operations are controlled by the two byte write select  
(BW[A:B]) and a write enable (WE) input. All writes are conducted  
with on-chip synchronous self timed write circuitry.  
■ Clock enable (CEN) pin to suspend operation  
■ Synchronous self timed writes  
Three synchronous chip enables (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output tri-state control. To avoid bus contention,  
the output drivers are synchronously tri-stated during the data  
portion of a write sequence.  
■ Asynchronous output enable  
■ Available in Pb-free 100-pin TQFP package  
■ Burst capability – linear or interleaved burst order  
■ Low standby power  
Logic Block Diagram  
ADDRESS  
REGISTER  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
MODE  
BURST  
LOGIC  
CE  
ADV/LD  
C
CLK  
CEN  
C
WRITE ADDRESS  
REGISTER  
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD  
A
B
U
F
MEMORY  
ARRAY  
BW  
A
WRITE  
DRIVERS  
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
S
T
E
E
R
I
DQs  
DQP  
DQP  
BW  
B
A
B
A
M
P
F
E
R
S
S
WE  
E
N
G
INPUT  
REGISTER  
E
OE  
READ LOGIC  
CE  
CE  
CE  
1
2
3
SLEEP  
CONTROL  
ZZ  
Errata: For information on silicon errata, see "Errata" on page 16. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-05515 Rev. *L  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 24, 2013  
1234567...19

中文翻译

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CY7C1353G-100AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1353G-100AXC CYPRESS

完全替代

 4-Mbit (256K x 18) Flow-through SRAM with NoB

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 		4-Mbit (256K x 18) Flow-through SRAM with NoB
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 		4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-133AXCT CYPRESS

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 		ZBT SRAM, 256KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, T
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 		4-Mbit (256K x 18) Flow-through SRAM with NoB
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 		256K x 36/512K x 18 Pipelined SRAM with NoBL⑩
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 		256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture

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