Datasheet > CY7C1353G_13

CY7C1353G_13

更新时间： 2024-11-26 12:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
19页	552K
描述
4-Mbit (256 K x 18) Flow-Through SRAM with NoBLâ¢ Architecture

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CY7C1353G_13 数据手册

CY7C1353G

4-Mbit (256 K × 18) Flow-Through SRAM

with NoBL™ Architecture

4-Mbit (256

K × 18) Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

■ Supports up to 100-MHz bus operations with zero wait states

❐ Data is transferred on every clock

The CY7C1353G is a 3.3 V, 256 K × 18 synchronous

flow-through burst SRAM designed specifically to support

unlimited true back-to-back read/write operations without the

insertion of wait states. The CY7C1353G is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to enable

consecutive read/write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of data through the SRAM, especially in systems that

require frequent write-read transitions.

■ Pin compatible and functionally equivalent to ZBT™ devices

■ Internally self timed output buffer control to eliminate the need

to use OE

■ Registered inputs for flow-through operation

■ Byte write capability

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

clock enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 8.0 ns (100-MHz device).

■ 256 K × 18 common I/O architecture

■ 2.5 V / 3.3 V I/O power supply (V_DDQ

)

■ Fast clock-to-output times

❐ 8.0 ns (for 100-MHz device)

Write operations are controlled by the two byte write select

(BW_[A:B]) and a write enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self timed writes

Three synchronous chip enables (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

■ Asynchronous output enable

■ Available in Pb-free 100-pin TQFP package

■ Burst capability – linear or interleaved burst order

■ Low standby power

Logic Block Diagram

ADDRESS

A0, A1, A

A1'

A0'

MODE

BURST

LOGIC

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

MEMORY

ARRAY

WRITE

DRIVERS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

DQs

DQP

INPUT

READ LOGIC

SLEEP

CONTROL

Errata: For information on silicon errata, see "Errata" on page 16. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

Document Number: 38-05515 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 24, 2013

12 3 4 5 6 7...19

中文翻译

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与CY7C1353G_13相关器件

型号	品牌	获取价格	描述	数据表
CY7C1353G-100AXC	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-100AXCT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 8ns, CMOS, PQFP100,
CY7C1353G-100AXI	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-117AXC	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-117AXI	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-133AXC	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-133AXCT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, T
CY7C1353G-133AXI	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1354A	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354A_04	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM with NoBL⑩

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