Datasheet > CY7C1353G

CY7C1353G

更新时间： 2024-11-26 05:19:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
13页	219K
描述
4-Mbit (256K x 18) Flow-through SRAM with NoBL⑩ Architecture

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CY7C1353G 数据手册

CY7C1353G

PRELIMINARY

4-Mbit (256K x 18) Flow-through SRAM

with NoBL™ Architecture

Functional Description^[1]

Features

• Can support up to 133-MHz bus operations with zero

wait states

The CY7C1353G is a 3.3V, 256K x 18 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1353G is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• 256K x 18 common I/O architecture

• 2.5V / 3.3V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

Write operations are controlled by the two Byte Write Select

(BW_[A:B]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

— 7.5 ns (for 117-MHz device)

— 8.0 ns (for 100-MHz device)

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• Pb-Free 100 TQFP package

• Burst Capability—linear or interleaved burst order

• Low standby power

Logic Block Diagram

ADDRESS

A0, A1, A

A1'

A0'

MODE

BURST

LOGIC

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

MEMORY

ARRAY

WRITE

DRIVERS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

DQs

DQP

INPUT

READ LOGIC

SLEEP

CONTROL

Note:

1.For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05515 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised October 22, 2004

12 3 4 5 6 7...13

中文翻译

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与CY7C1353G相关器件

型号	品牌	获取价格	描述	数据表
CY7C1353G_07	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G_12	CYPRESS	获取价格	4-Mbit (256 K Ã 18) Flow-Through SRAM with N
CY7C1353G_13	CYPRESS	获取价格	4-Mbit (256 K x 18) Flow-Through SRAM with No
CY7C1353G-100AXC	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-100AXCT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 8ns, CMOS, PQFP100,
CY7C1353G-100AXI	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-117AXC	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-117AXI	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-133AXC	CYPRESS	获取价格	4-Mbit (256K x 18) Flow-through SRAM with NoB
CY7C1353G-133AXCT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, T

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