CY7C1353-66AC

更新时间： 2024-11-26 05:19:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
13页	162K
描述
256Kx18 Flow-Through SRAM with NoBL Architecture

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CY7C1353-66AC 数据手册

1353

CY7C1353

256Kx18 Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

Pin compatible and functionally equivalent to ZBT

devices MCM63Z819 and MT55L256L18F

• Supports 66-MHz bus operations with zero wait states

— Data is transferred on every clock

•

The CY7C1353 is a 3.3V 256K by 18 Synchronous-

Flow-Through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1353 is equipped with the

advanced No Bus Latency (NoBL ) logic required to enable

consecutive Read/Write operations with data being transferred

on every clock cycle. This feature dramatically improves the

throughput of data through the SRAM, especially in systems

that require frequent Write-Read transitions.The CY7C1353 is

pin/functionally compatible to ZBT SRAMs MCM63Z819 and

MT55L256L18F.

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for Flow-Through operation

• Byte Write capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted sus-

pends operation and extends the previous clock cycle. Maxi-

mum access delay from the clock rise is 9.0 ns (66-MHz de-

vice).

• Fast clock-to-output times

— 11.0 ns (for 66-MHz device)

— 12.0 ns (for 50-MHz device)

— 14.0 ns (for 40-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

• Low standby power

Write operations are controlled by the four Byte Write Select

(BWS

) and a Write Enable (WE) input. All writes are con-

[1:0]

ducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

A_[17:0]

CEN

CONTROL

256KX18

and WRITE

LOGIC

MEMORY

DQ_[15:0]

ARRAY

DP_[1:0]

BWS

[1:0]

Mode

Selection Guide

7C1353-66

7C1353-50

12.0

7C1353-40

14.0

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Commercial

250 mA

5 mA

200 mA

5 mA

175 mA

5 mA

NoBL is a trademark of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 3, 1999

12 3 4 5 6 7...13

中文翻译

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与CY7C1353-66AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1353-66ACT	CYPRESS	获取价格	暂无描述
CY7C1353B	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-100AC	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-100ACT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1353B-117AC	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-117ACT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1353B-40AC	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-50AC	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-50BGC	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-66AC	CYPRESS	获取价格	256Kx18 Flow-Through SRAM with NoBL Architecture

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