Datasheet > 存储 > SRAM> CY7C1353B-66BGC

CY7C1353B-66BGC

更新时间： 2024-11-26 03:57:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	536K
描述
256Kx18 Flow-Through SRAM with NoBL Architecture

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技术参数
数据手册

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CY7C1353B-66BGC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA, BGA119,7X17,50
针数：	119	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.82	Base Number Matches：	1

CY7C1353B-66BGC 数据手册

353B

PRELIMINARY

CY7C1353B

256Kx18 Flow-Through SRAM with NoBL™ Architecture

Features

Functional Description

• Pin compatible and functionally equivalent to ZBT™

The CY7C1353B is a 3.3V, 256K by 18 Synchronous

Flow-Through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1353B is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to en-

able consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data through the SRAM, especially in sys-

tems that require frequent Write-Read transitions. The

CY7C1353B is pin/functionally compatible to ZBT SRAMs

MCM63Z819 and MT55L256L18F.

devices MCM63Z819 and MT55L256L18F

• Supports 117-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted sus-

pends operation and extends the previous clock cycle. Maxi-

mum access delay from the clock rise is 7.5 ns (117-MHz de-

vice).

• Fast clock-to-output times

— 7.5 ns (for 117- MHz device)

— 8.5 ns (for 100-MHz device)

— 11.0 ns (for 66-MHz device)

— 12.0 ns (for 50-MHz device)

Write operations are controlled by the four Byte Write Select

(BWS_[1:0]) and a Write Enable (WE) input. All writes are con-

ducted with on-chip synchronous self-timed write circuitry.

— 14.0 ns (for 40-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

• Low standby power

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

[17:0]

CEN

CONTROL

256KX18

and WRITE

LOGIC

MEMORY

[15:0]

[1:0]

ARRAY

BWS

[1:0]

Mode

Selection Guide

7C1353B-117 7C1353B-100 7C1353B-66 7C1353B-50 7C1353B-40

Maximum Access Time (ns)

Maximum Operating Current (mA) Commercial

7.5

375

8.5

350

11.0

250

12.0

200

14.0

175

Maximum CMOS Standby

Current (mA)

Commercial

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05266 Rev. **

Revised March 13, 2002

12 3 4 5 6 7...15

中文翻译

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与CY7C1353B-66BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1353C-100AXC	CYPRESS	获取价格	ZBT SRAM, 256KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1353C-100AXI	CYPRESS	获取价格	ZBT SRAM, 256KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1353C-133AXI	CYPRESS	获取价格	ZBT SRAM, 256KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP
CY7C1353F	CYPRESS	获取价格	4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-100AC	CYPRESS	获取价格	4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-100AI	CYPRESS	获取价格	4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-117AC	CYPRESS	获取价格	4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-117AI	CYPRESS	获取价格	4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-133AC	CYPRESS	获取价格	4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-133AI	CYPRESS	获取价格	4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture

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